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Contents

README

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TPS2350DR

Texas Instruments · Supervisor And Reset ICs · SOIC-14

TPS2350DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RTN power_in Supply return (ground) and positive supply input; for negative voltage systems it connects directly to the return node of the input power bus.
2 FLT output Open-drain, active-low fault indication that sinks up to 10 mA when in fault, withstands 80 V without leakage when not faulted, and is pulled to the lower of -VINA and -VINB.
3 UV input Under-voltage comparator input, typically driven from a divider between RTN and SOURCE, that enables the linear current amplifier when UV is more than 1.4 V above SOURCE.
4 OV input Over-voltage comparator input, typically driven from a divider between RTN and SOURCE, that disables the linear current amplifier when OV is 1.4 V or more above SOURCE.
5 FLTTIM bidirectional Fault timer pin where an external capacitor from FLTTIM to SOURCE sets the fault timeout, charged to the 4-V fault threshold and discharged at about 1% of the charge rate to set the retry duty cycle.
6 RAMP bidirectional Inrush slew-rate programming pin where an external capacitor between RAMP and SOURCE sets the turn-on current slew rate; when fully charged RAMP can exceed SOURCE by 6 V while the reference is clamped to 42 mV.
7 SOURCE bidirectional Negative current sense input connected to the sources of the supply-selector FETs and the negative terminal of the current sense resistor, which connects SOURCE to the more negative of -VINA and -VINB.
8 GATB output Gate drive for the external N-channel FET that selects -VINB; it is pulled 14 V above -VINB when -VINB is more negative than -VINA and pulled down to -VINA otherwise.
9 GATA output Gate drive for the external N-channel FET that selects -VINA; it is pulled 14 V above -VINA when -VINA is more negative than -VINB and pulled down to -VINB otherwise.
10 SENSE input Positive current sense input, used with a low-value resistor to SOURCE, that the linear current amplifier regulates to 42 mV and that trips the 120-mV overload threshold on fast faults.
11 GAT output Gate drive for the external N-channel protection MOSFET that ramps load current and disconnects on a fault, driven 14 V above SOURCE when fully enhanced.
12 PG output Open-drain, active-high power-good output indicating the power FET is fully enhanced; it sinks up to 10 mA, withstands 80 V without leakage when power is not good, and is pulled to the lower of -VINA and -VINB.
13 -VINB power_in Negative supply input B, connected directly to the second input supply negative rail (recommended supply -12 V to -80 V with respect to RTN).
14 -VINA power_in Negative supply input A, connected directly to the first input supply negative rail (recommended supply -12 V to -80 V with respect to RTN).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Power Management (PMIC)
Pins 14

CAD (KiCad official)

  • Symbol: TPS2350DR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: tps2350dr-etched.step / tps2350dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps2350dr.step / tps2350dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 99780b23bedb684a, retrieved 2026-10-08, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF