component
CD4069UBE
Public Made by Adomby adom
Texas Instruments Inverters, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4069UBE
Texas Instruments · Inverters · DIP-14
CD4069UBE from Texas Instruments, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Inverter input stage 1; accepts logic voltage from -0.5V to VDD+0.5V per Absolute Maximum Ratings |
| 2 | G = A | output | Inverter output stage 1; provides inverted logic signal with propagation delay tPHL/tPLH of 30ns typical at 10V |
| 3 | B | input | Inverter input stage 2; accepts logic voltage from -0.5V to VDD+0.5V per Absolute Maximum Ratings |
| 4 | H = B | output | Inverter output stage 2; provides inverted logic signal with propagation delay tPHL/tPLH of 30ns typical at 10V |
| 5 | C | input | Inverter input stage 3; accepts logic voltage from -0.5V to VDD+0.5V per Absolute Maximum Ratings |
| 6 | I = C | output | Inverter output stage 3; provides inverted logic signal with propagation delay tPHL/tPLH of 30ns typical at 10V |
| 7 | VSS | power_in | Negative supply connection and ground reference for device operation |
| 8 | J = D | output | Inverter output stage 4; provides inverted logic signal with propagation delay tPHL/tPLH of 30ns typical at 10V |
| 9 | D | input | Inverter input stage 4; accepts logic voltage from -0.5V to VDD+0.5V per Absolute Maximum Ratings |
| 10 | K = E | output | Inverter output stage 5; provides inverted logic signal with propagation delay tPHL/tPLH of 30ns typical at 10V |
| 11 | E | input | Inverter input stage 5; accepts logic voltage from -0.5V to VDD+0.5V per Absolute Maximum Ratings |
| 12 | L = F | output | Inverter output stage 6; provides inverted logic signal with propagation delay tPHL/tPLH of 30ns typical at 10V |
| 13 | F | input | Inverter input stage 6; accepts logic voltage from -0.5V to VDD+0.5V per Absolute Maximum Ratings |
| 14 | VDD | power_in | Positive supply voltage with recommended operating range of 3V to 18V and absolute maximum rating of 20V |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD4069UBE - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
cd4069ube-etched.step/cd4069ube-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4069ube.step/cd4069ube.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (34 pp, sha256
5f18da9e2683e36e, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).