component

AD5141WBCPZ10-RL7

Public Made by Adom

by adom

Analog Devices Digital Potentiometers, LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5141wbcpz10-rl7factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

AD5141WBCPZ10-RL7

Analog Devices · Digital Potentiometers · LFCSP-16(3x3)

AD5141WBCPZ10-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin, serves as the logic ground reference.
2 A passive Terminal A of the RDAC, with VSS ≤ VA ≤ VDD.
3 W passive Wiper terminal of the RDAC, with VSS ≤ VW ≤ VDD.
4 B passive Terminal B of the RDAC, with VSS ≤ VB ≤ VDD.
5 VSS power_in Negative power supply; decouple with 0.1 µF ceramic and 10 µF capacitors.
6 SYNC/ADDR0 input Programmable address ADDR0 for multiple package decoding when DIS = 1; active-low synchronization data input when DIS = 0, where data loads into the RDAC register on SYNC returning high.
7 RESET input Hardware reset that refreshes the RDAC registers from EEPROM, activated at logic low; tie to VLOGIC if unused.
8 DIS input Digital interface select, selecting SPI when tied to GND (DIS = 0) and I2C when tied to VLOGIC (DIS = 1); this pin cannot be left floating.
9 VDD power_in Positive power supply; decouple with 0.1 µF ceramic and 10 µF capacitors.
10 VLOGIC power_in Logic power supply from 1.8 V to VDD; decouple with 0.1 µF ceramic and 10 µF capacitors.
11 SCLK/SCL input SPI serial clock (SCLK) or I2C serial clock (SCL), with data clocked in at logic low transition.
12 SDI/SDA bidirectional Serial data input (SDI) when DIS = 0 and serial data input/output (SDA) when DIS = 1.
13 WP input Optional write protect, active at logic low, that prevents changes to RDAC and EEPROM contents except when reloading EEPROM into the RDAC register; tie to VLOGIC if unused.
14 SDO/ADDR1 output Programmable address ADDR1 for multiple package decoding when DIS = 1; open-drain serial data output requiring an external pull-up resistor when DIS = 0.
15 INDEP input Linear gain setting mode at power-up, loading each string resistor from its associated memory location; once enabled it cannot be disabled by software.
16 LRDAC input Load RDAC, activated low, transferring the input register contents to the RDAC register for asynchronous update; tie to VLOGIC if unused.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-16(3x3)
Category ADC/DAC/Data Conversion
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Nominal Resistor Tolerance ΔRAB/RAB -8 1 8 % RAB = 10 kΩ 5
Resistor Integral Nonlinearity R-INL -2 0.2 2 LSB RAB = 10 kΩ, VDD ≥ 2.7 V 5
Resistor Integral Nonlinearity R-INL -5 1.5 5 LSB RAB = 10 kΩ, VDD < 2.7 V 5
Resistor Differential Nonlinearity R-DNL -0.5 0.2 0.5 LSB 5
Integral Nonlinearity INL -1 0.2 1 LSB RAB = 10 kΩ 5
Differential Nonlinearity DNL -0.5 0.2 0.5 LSB 5
Full-Scale Error VWFSE -2.5 -0.1 LSB RAB = 10 kΩ 5
Zero-Scale Error VWZSE 1.2 3 LSB RAB = 10 kΩ 6
Voltage Divider Temperature Coefficient (ΔVW/VW)/ΔT × 10^6 -5 5 ppm/°C Code = half scale 6
Resistance Temperature Coefficient (ΔRAB/RAB)/ΔT × 10^6 35 ppm/°C Code = full scale 5
Wiper Resistance RW 55 125 Ω Code = zero scale, RAB = 10 kΩ 5
Bottom Scale or Top Scale Wiper Resistance RBS or RTS 40 80 Ω RAB = 10 kΩ 5
Maximum Continuous Current IA, IB, IW IA, IB, IW -6 6 mA RAB = 10 kΩ 6
Capacitance A, Capacitance B CA, CB 25 pF f = 1 MHz, measured to GND, code = half scale, RAB = 10 kΩ 6
Capacitance W CW 12 pF f = 1 MHz, measured to GND, code = half scale, RAB = 10 kΩ 6
Common-Mode Leakage Current -500 15 500 nA VA = VW = VB 6
Input Logic High VINH 0.8 × VLOGIC VLOGIC = 1.8 V to 2.3 V 6
Input Logic High VINH 0.7 × VLOGIC VLOGIC = 2.3 V to 5.5 V 6
Input Logic Low VINL 0.2 × VLOGIC 6
Input Hysteresis VHYST 0.1 × VLOGIC 6
Input Current IIN -1 1 µA 6
Input Capacitance CIN 5 pF 6
Output Low Voltage VOL 0.4 V ISINK = 3 mA 6
Output Low Voltage VOL 0.6 V ISINK = 6 mA, VLOGIC > 2.3 V 6
Three-State Leakage Current -1 1 µA 6
Three-State Output Capacitance 2 pF 6
Single-Supply Power Range VDD / VSS 2.3 5.5 V VSS = GND 6
Dual-Supply Power Range VDD / VSS 2.25 2.75 V Dual supply, VSS = -2.25 V to -2.75 V 6
Logic Supply Range VLOGIC 1.8 V Single supply, VSS = GND; upper limit VDD 6
Positive Supply Current IDD 0.7 5.5 µA VIH = VLOGIC or VIL = GND, VDD = 5.5 V 6
Positive Supply Current IDD 400 nA VIH = VLOGIC or VIL = GND, VDD = 2.3 V 6
Negative Supply Current ISS -5.5 -0.7 µA VIH = VLOGIC or VIL = GND 6
EEPROM Store Current IDD_EEPROM_STORE 2 mA VIH = VLOGIC or VIL = GND 6
EEPROM Read Current IDD_EEPROM_READ 320 µA VIH = VLOGIC or VIL = GND 6
Logic Supply Current ILOGIC 0.05 1.4 µA VIH = VLOGIC or VIL = GND 6
Power Dissipation PDISS 3.5 µW VIH = VLOGIC or VIL = GND 6
Power Supply Rejection Ratio PSRR -66 -60 dB ΔVDD/ΔVSS = VDD ± 10%, code = full scale 6
Bandwidth -3 dB BW 3 MHz RAB = 10 kΩ 7
Total Harmonic Distortion THD -80 dB VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ 7
Resistor Noise Density eN_WB 7 nV/√Hz Code = half scale, TA = 25°C, f = 10 kHz, RAB = 10 kΩ 7
VW Settling Time tS 2 µs VA = 5 V, VB = 0 V, zero scale to full scale, ±0.5 LSB, RAB = 10 kΩ 7
Data Retention 50 years 7
VDD to GND VDD -0.3 7 V 11
VSS to GND VSS -7 0.3 V 11
VDD to VSS VDD - VSS 7 V 11
VLOGIC to GND VLOGIC -0.3 7 V Lower of VDD + 0.3 V or +7.0 V 11
Digital Inputs -0.3 7 V Lower of VLOGIC + 0.3 V or +7 V 11
Pulsed Current IA, IW, IB IA, IW, IB -6 6 mA/d RAW = 10 kΩ, frequency > 10 kHz, d = pulse duty factor 11
Pulsed Current IA, IW, IB IA, IW, IB -6 6 mA/√d RAW = 10 kΩ, frequency ≤ 10 kHz, d = pulse duty factor 11
Operating Temperature Range TA -40 125 °C Includes programming of EEPROM memory 11
Maximum Junction Temperature TJ 150 °C 11
Storage Temperature Range -65 150 °C 11
Reflow Soldering Peak Temperature 260 °C Time at peak 20 s to 40 s 11
Thermal Resistance Junction to Ambient, 16-Lead LFCSP θJA 75.4 °C/W JEDEC natural convection 11
Thermal Resistance Junction to Board, 16-Lead LFCSP θJB 33.4 °C/W JEDEC θJB environment 11

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper EPAD Exposed Pad. Connect this exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper plan 12

CAD (KiCad official)

  • Symbol: AD5141WBCPZ10-RL7
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
  • 3D model files: ad5141wbcpz10-rl7-etched.step / ad5141wbcpz10-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5141wbcpz10-rl7.step / ad5141wbcpz10-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (30 pp, sha256 9e0c5cdca83084fb, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF