Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

CDC421A250RGER

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · VQFN-24-EP(4x4)

CDC421A250RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CE input Chip enable LVCMOS input: CE = 1 enables the device and outputs; CE = 0 disables all current sources so LVPECL outputs are Hi-Z.
2 NC unconnected TI test pin; do not connect, leave floating.
3 NC unconnected TI test pin; do not connect, leave floating.
4 NC unconnected TI test pin; do not connect, leave floating.
5 NC unconnected TI test pin; do not connect, leave floating.
6 NC unconnected TI test pin; do not connect, leave floating.
7 OUTN output High-speed negative differential LVPECL output, enabled by the CE pin.
8 GND power_in Ground.
9 GND power_in Ground.
10 OUTP output High-speed positive differential LVPECL output, enabled by the CE pin.
11 NC unconnected TI test pin; do not connect, leave floating.
12 NC unconnected TI test pin; do not connect, leave floating.
13 NC unconnected TI test pin; do not connect, leave floating.
14 NC unconnected TI test pin; do not connect, leave floating.
15 NC unconnected TI test pin; do not connect, leave floating.
16 VCC power_in 3.3-V power supply; recommended operating range 3.0 V to 3.6 V.
17 VCC power_in 3.3-V power supply; recommended operating range 3.0 V to 3.6 V.
18 NC unconnected TI test pin; do not connect, leave floating.
19 NC unconnected TI test pin; do not connect, leave floating.
20 NC unconnected TI test pin; do not connect, leave floating.
21 XIN1 input In crystal mode, connect to one end of the crystal (XIN2 to the other end); in LVCMOS single-ended driven mode, this pin is the input reference.
22 XIN2 input In crystal mode, connect to the other end of the crystal; in LVCMOS single-ended driven mode, connect to GND.
23 NC unconnected TI test pin; do not connect, leave floating.
24 NC unconnected TI test pin; do not connect, leave floating.
25 Thermal pad passive Exposed thermal pad on the package bottom; must be soldered to the PCB for thermal and mechanical performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Clock/Timing
Pins 25

CAD (KiCad official)

  • Symbol: CDC421A250RGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: cdc421a250rger-etched.step / cdc421a250rger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdc421a250rger.step / cdc421a250rger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (17 pp, sha256 915ca5742046cc8c, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF