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ISL28022FRZ-T

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RENESAS Supervisor And Reset ICs, QFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)isl28022frz-tfactory-2.0.0extractor-text
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Contents

README

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ISL28022FRZ-T

RENESAS · Supervisor And Reset ICs · QFN-16(3x3)

ISL28022FRZ-T from RENESAS, in a QFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input I2C/SMBus address select bit 1, one of two address-select pins with four selectable levels (VCC, GND, SCL/SMBCLK, SDA/SMBDAT) for 16 address combinations.
2 A0 input I2C/SMBus address select bit 0, one of two address-select pins with four selectable levels (VCC, GND, SCL/SMBCLK, SDA/SMBDAT) for 16 address combinations.
3 EXT_CLK/INT bidirectional External ADC clock input or CPU interrupt output; when configured as an interrupt the output is open drain and requires a pull-up to a supply of up to 20V.
4 SDA/SMBDAT bidirectional I2C serial data input/output, an open-drain pin that requires a pull-up resistor connected to the device VCC.
5 SCL/SMBCLK input I2C serial clock input that clocks all data to and from the device.
6 NC unconnected No connect; no internal connection.
7 NC unconnected No connect; no internal connection.
8 NC unconnected No connect; no internal connection.
9 VCC power_in Positive supply pin for the analog circuitry, operating over a 3V to 5.5V chip supply range.
10 GND power_in Negative power pin that can be connected to ground or to a negative voltage (most negative supply in dual-supply applications).
11 VBUS power_in Bus voltage sense input, which should be connected to the supply bus to be monitored over a 0V to 60V range.
12 VINM input Current sense minus input, connected to the most negative side of the current shunt resistor.
13 VINP input Current sense plus input, connected to the most positive side of the current shunt resistor.
14 NC unconnected No connect; no internal connection.
15 NC unconnected No connect; no internal connection.
16 NC unconnected No connect; no internal connection.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer RENESAS
Package QFN-16(3x3)
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VSENSE differential full-scale range, PGA gain /1 VSENSEDIFF 0 40 mV PGA gain = /1 6
VSENSE differential full-scale range, PGA gain /2 VSENSEDIFF 0 80 mV PGA gain = /2 6
VSENSE differential full-scale range, PGA gain /4 VSENSEDIFF 0 160 mV PGA gain = /4 6
VSENSE differential full-scale range, PGA gain /8 VSENSEDIFF 0 320 mV PGA gain = /8 6
Current sense common-mode voltage (VINP, VINM) VCMSENSE 0 60 V 6
VSENSE offset voltage VOS -75 10 75 µV PGA gain = /1, /2, /4, /8; ADC setting = 1111 6
VSENSE VOS vs common-mode CMRR CMRR 110 130 dB VBUS = 0V to 60V; BRNG = 2, 3 6
Current sense gain error ACS -40 40 m% 6
Current sense gain error temperature coefficient ACSTC -1 1 m%/°C 6
Input leakage, VIN pins (VINP and VINM) IVINACT -20 20 µA Active mode (for both VINP and VINM pins) 6
Input leakage, VIN pins (VINP and VINM) IVINACT -0.5 0.1 0.5 µA Power-down mode (for both VINP and VINM pins) 6
Useful bus voltage range VBUS 0 16 V BRNG = 0 6
Useful bus voltage range VBUS 0 32 V BRNG = 1 6
Useful bus voltage range VBUS 0 60 V BRNG = 2, 3 6
Current measurement error -0.3 0.2 0.3 % TA = +25°C 7
Current measurement error over temperature -0.5 0.5 % TA = -40°C to +85°C 7
Current measurement error over temperature -1 1 % TA = -40°C to +125°C 7
Bus voltage measurement error -0.3 0.2 0.3 % TA = +25°C 7
Bus voltage measurement error over temperature -0.5 0.5 % TA = -40°C to +85°C 7
Bus voltage measurement error over temperature -1 1 % TA = -40°C to +125°C 7
ADC conversion time ts 72 79.2 µs Mode = 5 or 6; ADC setting = 0000 7
ADC conversion time ts 132 145.2 µs Mode = 5 or 6; ADC setting = 0001 7
ADC conversion time ts 258 283.8 µs Mode = 5 or 6; ADC setting = 0010 7
ADC conversion time ts 508 558.8 µs Mode = 5 or 6; ADC setting = 0011 7
ADC conversion time ts 1.01 1.11 ms Mode = 5 or 6; ADC setting = 1001 7
ADC conversion time ts 2.01 2.21 ms Mode = 5 or 6; ADC setting = 1010 7
ADC conversion time ts 4.01 4.41 ms Mode = 5 or 6; ADC setting = 1011 7
ADC conversion time ts 8.01 8.81 ms Mode = 5 or 6; ADC setting = 1100 7
ADC conversion time ts 16.01 17.61 ms Mode = 5 or 6; ADC setting = 1101 7
ADC conversion time ts 32.01 35.21 ms Mode = 5 or 6; ADC setting = 1110 7
ADC conversion time ts 64.01 70.41 ms Mode = 5 or 6; ADC setting = 1111 7
SDA and SCL input buffer LOW voltage VIL -0.3 V Maximum printed as 0.3 x VCC 7
SDA output buffer LOW voltage, sinking 3mA VOL 0 0.02 0.4 V VCC = 5V, IOL = 3mA 7
Supply voltage absolute maximum VCC 6 V 6
VBUS voltage absolute maximum 63 V 6
Common-mode input voltage absolute maximum (VINP, VINM) 63 V 6
Differential input voltage absolute maximum (VINP, VINM) -63 63 V 6
Input voltage absolute maximum (digital pins) -0.3 5.5 V Printed as (GND - 0.3V) to 5.5V 6
Open-drain output current 10 mA 6
Open-drain voltage (interrupt) 24 V 6
ESD rating, Human Body Model 8 kV Tested per JESD22-A114 6
Maximum storage temperature range -65 150 °C 6
Maximum junction temperature (TJMAX) TJMAX 150 °C 6
Thermal resistance, junction to ambient, 16 Ld QFN JA 52 °C/W 16 Ld QFN (Notes 4, 5) 6
Thermal resistance, junction to case, 16 Ld QFN JC 6.5 °C/W 16 Ld QFN (Notes 4, 5) 6
Ambient temperature range (TA) TA -40 125 °C 6
SCL operating frequency fSCL 0.001 3.4 MHz 23
Repeated START condition setup time tSUSTA 160 ns 23
Hold time after repeated START condition tHDSTA 160 ns 23
SCL clock low period tLOW 160 ns 23
SCL clock high period tHIGH 60 ns 23
Data setup time tSUDAT 10 ns 23
Data hold time tHDDAT 10 70 ns 23
Clock rise time trCL 10 40 ns 23
Clock rise time after a repeated START condition and after an acknowledge bit trCL1 10 80 ns 23
Clock fall time tfCL 10 40 ns 23
Data rise time trDA 10 80 ns 23
Data fall time tfDA 10 80 ns 23
STOP condition setup time tSUSTO 160 ns 23

CAD (KiCad official)

  • Symbol: ISL28022FRZ-T
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: QFN-16(3x3) (KiCad packages3D, STEP)
  • 3D model files: isl28022frz-t-etched.step / isl28022frz-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isl28022frz-t.step / isl28022frz-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (34 pp, sha256 eb35eab1e3f3740d, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF