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SN74LVTH241PWR

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Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LVTH241PWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

SN74LVTH241PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-low output enable for the 1Y outputs; when 1OE is high the 1Y outputs are in the high-impedance state.
2 1A1 input Data input for channel 1A1 with active bus-hold, which holds an unused or undriven input at a valid logic state.
3 2Y4 tri_state Noninverting 3-state output of channel 2Y4 that is high-impedance when 2OE is low.
4 1A2 input Data input for channel 1A2 with active bus-hold, which holds an unused or undriven input at a valid logic state.
5 2Y3 tri_state Noninverting 3-state output of channel 2Y3 that is high-impedance when 2OE is low.
6 1A3 input Data input for channel 1A3 with active bus-hold, which holds an unused or undriven input at a valid logic state.
7 2Y2 tri_state Noninverting 3-state output of channel 2Y2 that is high-impedance when 2OE is low.
8 1A4 input Data input for channel 1A4 with active bus-hold, which holds an unused or undriven input at a valid logic state.
9 2Y1 tri_state Noninverting 3-state output of channel 2Y1 that is high-impedance when 2OE is low.
10 GND power_in Ground reference pin for the device.
11 2A1 input Data input for channel 2A1 with active bus-hold, which holds an unused or undriven input at a valid logic state.
12 1Y4 tri_state Noninverting 3-state output of channel 1Y4 that is high-impedance when 1OE is high.
13 2A2 input Data input for channel 2A2 with active bus-hold, which holds an unused or undriven input at a valid logic state.
14 1Y3 tri_state Noninverting 3-state output of channel 1Y3 that is high-impedance when 1OE is high.
15 2A3 input Data input for channel 2A3 with active bus-hold, which holds an unused or undriven input at a valid logic state.
16 1Y2 tri_state Noninverting 3-state output of channel 1Y2 that is high-impedance when 1OE is high.
17 2A4 input Data input for channel 2A4 with active bus-hold, which holds an unused or undriven input at a valid logic state.
18 1Y1 tri_state Noninverting 3-state output of channel 1Y1 that is high-impedance when 1OE is high.
19 2OE input Active-high output enable for the 2Y outputs; when 2OE is low the 2Y outputs are in the high-impedance state.
20 VCC power_in Supply voltage pin; the recommended operating range is 2.7 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2.7 3.6 V 3
High-level input voltage VIH 2 V 3
Low-level input voltage VIL 0.8 V 3
Input voltage VI 5.5 V 3
High-level output current IOH -32 mA 3
Low-level output current IOL 64 mA 3
Input transition rise or fall rate ∆t/∆v 10 ns/V Outputs enabled 3
Power-up ramp rate ∆t/∆VCC 200 µs/V 3
Operating free-air temperature TA -40 85 °C SN74LVTH241 3
Supply voltage range VCC -0.5 4.6 V 3
Input voltage range VI -0.5 7 V see Note 1 3
Voltage applied to any output in high-impedance or power-off state VO -0.5 7 V 3
Voltage applied to any output in high state VO -0.5 V upper limit printed as VCC + 0.5 V 3
Current into any output in low state IO 128 mA SN74LVTH241 3
Current into any output in high state IO 64 mA SN74LVTH241; see Note 2 3
Input clamp current IIK -50 mA VI < 0 3
Output clamp current IOK -50 mA VO < 0 3
Storage temperature range Tstg -65 150 °C 3
Input clamp voltage VIK -1.2 V VCC = 2.7 V, II = −18 mA 4
High-level output voltage VOH 2.4 V VCC = 2.7 V, IOH = −8 mA 4
High-level output voltage VOH 2 V VCC = 3 V, IOH = −32 mA 4
Low-level output voltage VOL 0.2 V VCC = 2.7 V, IOL = 100 µA 4
Low-level output voltage VOL 0.5 V VCC = 2.7 V, IOL = 24 mA 4
Low-level output voltage VOL 0.4 V IOL = 16 mA 4
Low-level output voltage VOL 0.55 V VCC = 3 V, IOL = 64 mA 4
Input current II 10 µA VCC = 0 or 3.6 V, VI = 5.5 V 4
Control inputs input current II -1 1 µA VCC = 3.6 V, VI = VCC or GND 4
Data inputs input current II 1 µA VCC = 3.6 V, VI = VCC 4
Data inputs input current II -5 µA VCC = 3.6 V, VI = 0 4
Power-off input/output current Ioff -100 100 µA VCC = 0, VI or VO = 0 to 4.5 V 4
Bus-hold current, data inputs II(hold) 75 µA VCC = 3 V, VI = 0.8 V 4
Bus-hold current, data inputs II(hold) -75 µA VCC = 3 V, VI = 2 V 4
Bus-hold maximum dynamic current, data inputs II(hold) -750 500 µA VCC = 3.6 V, VI = 0 to 3.6 V 4
Off-state high-level output current IOZH 5 µA VCC = 3.6 V, VO = 3 V 4
Off-state low-level output current IOZL -5 µA VCC = 3.6 V, VO = 0.5 V 4
Power-up high-impedance output current IOZPU -100 100 µA VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE/OE = don't care 4
Power-down high-impedance output current IOZPD -100 100 µA VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE/OE = don't care 4
Supply current, outputs high ICC 0.19 mA VCC = 3.6 V, IO = 0, VI = VCC or GND 4
Supply current, outputs low ICC 5 mA VCC = 3.6 V, IO = 0, VI = VCC or GND 4
Supply current, outputs disabled ICC 0.19 mA VCC = 3.6 V, IO = 0, VI = VCC or GND 4
Supply current increase per input at TTL level ∆ICC 0.2 mA VCC = 3 V to 3.6 V, one input at VCC − 0.6 V, other inputs at VCC or GND 4
Input capacitance Ci 3 pF VI = 3 V or 0 4
Output capacitance Co 7 pF VO = 3 V or 0 4
Propagation delay low-to-high, A to Y tPLH 1.1 2.3 3.5 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Propagation delay low-to-high, A to Y tPLH 3.9 ns VCC = 2.7 V, CL = 50 pF 5
Propagation delay high-to-low, A to Y tPHL 1.3 2.2 3.4 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Propagation delay high-to-low, A to Y tPHL 3.6 ns VCC = 2.7 V, CL = 50 pF 5
Enable time low-to-high, OE to Y tPZH 1.1 2.7 4.5 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Enable time low-to-high, OE to Y tPZH 5.4 ns VCC = 2.7 V, CL = 50 pF 5
Enable time high-to-low, OE to Y tPZL 1.4 2.9 4.4 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Enable time high-to-low, OE to Y tPZL 5 ns VCC = 2.7 V, CL = 50 pF 5
Disable time low-to-high, OE to Y tPHZ 1.6 2.8 4.5 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Disable time low-to-high, OE to Y tPHZ 5.3 ns VCC = 2.7 V, CL = 50 pF 5
Disable time high-to-low, OE to Y tPLZ 1.8 3 4.7 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Disable time high-to-low, OE to Y tPLZ 5.2 ns VCC = 2.7 V, CL = 50 pF 5
Package thermal impedance, PW package θJA 83 °C/W PW package, per JESD 51-7 3

CAD (KiCad official)

  • Symbol: SN74LVTH241PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lvth241pwr-etched.step / sn74lvth241pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvth241pwr.step / sn74lvth241pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 4be4674fefc59ecf, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF