component
SN74HC573PW
Public Made by Adomby adom
lingxingic Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC573PW
lingxingic · Latches · TSSOP-20
SN74HC573PW from lingxingic, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Three-state output enable input (active low); high level places outputs in high-impedance state |
| 2 | D0 | input | Data input bit 0; latched when LE transitions low |
| 3 | D1 | input | Data input bit 1; latched when LE transitions low |
| 4 | D2 | input | Data input bit 2; latched when LE transitions low |
| 5 | D3 | input | Data input bit 3; latched when LE transitions low |
| 6 | D4 | input | Data input bit 4; latched when LE transitions low |
| 7 | D5 | input | Data input bit 5; latched when LE transitions low |
| 8 | D6 | input | Data input bit 6; latched when LE transitions low |
| 9 | D7 | input | Data input bit 7; latched when LE transitions low |
| 10 | GND | power_in | Ground reference (0V) |
| 11 | LE | input | Latch enable input (active high); high level enables transparent mode, data latched on falling edge |
| 12 | Q7 | tri_state | Three-state latch output bit 7; high-impedance when OE is high |
| 13 | Q6 | tri_state | Three-state latch output bit 6; high-impedance when OE is high |
| 14 | Q5 | tri_state | Three-state latch output bit 5; high-impedance when OE is high |
| 15 | Q4 | tri_state | Three-state latch output bit 4; high-impedance when OE is high |
| 16 | Q3 | tri_state | Three-state latch output bit 3; high-impedance when OE is high |
| 17 | Q2 | tri_state | Three-state latch output bit 2; high-impedance when OE is high |
| 18 | Q1 | tri_state | Three-state latch output bit 1; high-impedance when OE is high |
| 19 | Q0 | tri_state | Three-state latch output bit 0; high-impedance when OE is high |
| 20 | VCC | power_in | Supply voltage operating from 2.0V to 6.0V for SN74HC573 or 4.5V to 5.5V for SN74HCT573 |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74HC573PW - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74hc573pw-etched.step/sn74hc573pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc573pw.step/sn74hc573pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (21 pp, sha256
1e9be54d60bf08ab, retrieved 2026-09-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).