component
TLE5012BE1000XUMA1
Public Made by Adomby adom
Infineon Technologies , SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTLE5012BE1000XUMA1
Infineon Technologies · IC · SOIC-8
TLE5012BE1000XUMA1 from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IFC | bidirectional | Interface C (CLK / IIF_IDX / HS3): external clock, IIF index or Hall switch signal 3; external clock is not available in IIF or HSM interface mode. |
| 2 | SCK | input | SSC clock input. |
| 3 | CSQ | input | SSC chip select input. |
| 4 | DATA | bidirectional | SSC data input/output. |
| 5 | IFA | bidirectional | Interface A (IIF_A / HS1 / PWM / SPC): IIF phase A, Hall switch signal 1, PWM or SPC output (input for SPC trigger only). |
| 6 | VDD | power_in | Supply voltage; application circuits show 3.0 - 5.5V with a 100nF capacitor. |
| 7 | GND | power_in | Ground. |
| 8 | IFB | output | Interface B (IIF_B / HS2): IIF phase B or Hall switch signal 2. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-8 |
| Category | |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 3 | 5 | 5.5 | V | Directly blocked with 100-nF ceramic capacitor | 16 |
| Supply current | IDD | 14 | 16 | mA | 16 | ||
| Magnetic induction | BXY | 30 | 50 | mT | -40°C < TJ < 150°C | 16 | |
| Magnetic induction | BXY | 30 | 60 | mT | -40°C < TJ < 100°C | 16 | |
| Magnetic induction | BXY | 30 | 70 | mT | -40°C < TJ < 85°C | 16 | |
| Extended magnetic induction range | BXY | 25 | 30 | mT | Additional angle error of 0.1° | 16 | |
| Angle range | Ang | 0 | 360 | ° | 16 | ||
| POR level | VPOR | 2 | 2.9 | V | Power-on reset | 16 | |
| POR hysteresis | VPORhy | 30 | mV | 16 | |||
| Power-on time | tPon | 5 | 7 | ms | VDD > VDDmin | 17 | |
| Fast Reset time | tRfast | 0.5 | ms | Fast reset is triggered by disabling startup BIST (S_BIST = 0), then enabling chip reset (AS_RST = 1) | 17 | ||
| Voltage on VDD pin | VDD | -0.5 | 6.5 | V | Max 40 h/Lifetime | 16 | |
| Voltage on any pin | VIN | -0.5 | 6.5 | V | 16 | ||
| Voltage on any pin (relative to VDD) | VIN | 0.5 | V | VDD + 0.5 V | 16 | ||
| Junction temperature | TJ | -40 | 150 | °C | 16 | ||
| Junction temperature | TJ | 150 | °C | For 1000 h, not additive | 16 | ||
| Magnetic field induction | B | 200 | mT | Max. 5 min @ TA = 25°C | 16 | ||
| Magnetic field induction | B | 150 | mT | Max. 5 h @ TA = 25°C | 16 | ||
| Storage temperature | TST | -40 | 150 | °C | Without magnetic field | 16 | |
| Input voltage | VIN | -0.3 | 5.5 | V | 18 | ||
| Output current (DATA) | IQ | -25 | mA | PAD_DRV='0x', sink current, VDD = 5 V | 18 | ||
| Output current (DATA) | IQ | -5 | mA | PAD_DRV='10', sink current, VDD = 5 V | 18 | ||
| Output current (DATA) | IQ | -0.4 | mA | PAD_DRV='11', sink current, VDD = 5 V | 18 | ||
| Output current (IFA/IFB/IFC) | IQ | -15 | mA | PAD_DRV='0x', sink current, VDD = 5 V | 18 | ||
| Output current (IFA/IFB/IFC) | IQ | -5 | mA | PAD_DRV='1x', sink current, VDD = 5 V | 18 | ||
| Output rise/fall time | tfall, trise | 8 | ns | DATA, 50 pF, PAD_DRV='00' | 18 | ||
| Output rise/fall time | tfall, trise | 28 | ns | DATA, 50 pF, PAD_DRV='01' | 18 | ||
| Output rise/fall time | tfall, trise | 45 | ns | DATA, 50 pF, PAD_DRV='10' | 18 | ||
| Output rise/fall time | tfall, trise | 130 | ns | DATA, 50 pF, PAD_DRV='11' | 18 | ||
| Output rise/fall time | tfall, trise | 15 | ns | IFA/IFB, 20 pF, PAD_DRV='0x' | 18 | ||
| Output rise/fall time | tfall, trise | 30 | ns | IFA/IFB, 20 pF, PAD_DRV='1x' | 18 | ||
| Input signal low-level (4.5 V < VDD < 5.5 V) | VL5 | 0.3 | V | 0.3 VDD | 19 | ||
| Input signal high level (4.5 V < VDD < 5.5 V) | VH5 | 0.7 | V | 0.7 VDD | 19 | ||
| Output signal low-level (4.5 V < VDD < 5.5 V) | VOL5 | 1 | V | DATA; IQ = -25 mA (PAD_DRV='0x'), IQ = -5 mA (PAD_DRV='10'), IQ = -0.4 mA (PAD_DRV='11') | 19 | ||
| Pull-up current (4.5 V < VDD < 5.5 V) | IPU | -225 | -10 | µA | CSQ | 19 | |
| Pull-up current (4.5 V < VDD < 5.5 V) | IPU | -150 | -10 | µA | DATA | 19 | |
| Pull-down current (4.5 V < VDD < 5.5 V) | IPD | 10 | 225 | µA | SCK | 19 | |
| Pull-down current (4.5 V < VDD < 5.5 V) | IPD | 10 | 150 | µA | IFA, IFB, IFC | 19 | |
| Input signal low-level (3.0 V < VDD < 3.6 V) | VL3 | 0.3 | V | 0.3 VDD | 19 | ||
| Input signal high level (3.0 V < VDD < 3.6 V) | VH3 | 0.7 | V | 0.7 VDD | 19 | ||
| Output signal low-level (3.0 V < VDD < 3.6 V) | VOL3 | 0.9 | V | DATA; IQ = -15 mA (PAD_DRV='0x'), IQ = -3 mA (PAD_DRV='10'), IQ = -0.24 mA (PAD_DRV='11') | 19 | ||
| Pull-up current (3.0 V < VDD < 3.6 V) | IPU | -225 | -3 | µA | CSQ | 19 | |
| Pull-up current (3.0 V < VDD < 3.6 V) | IPU | -150 | -3 | µA | DATA | 19 | |
| Pull-down current (3.0 V < VDD < 3.6 V) | IPD | 3 | 225 | µA | SCK | 19 | |
| Pull-down current (3.0 V < VDD < 3.6 V) | IPD | 3 | 150 | µA | IFA, IFB, IFC | 19 | |
| ESD voltage HBM | VHBM | -4 | 4 | kV | Human Body Model | 20 | |
| ESD voltage SDM | VSDM | -0.5 | 0.5 | kV | Socketed Device Model | 20 | |
| X, Y output range | RGADC | -23230 | 23230 | digits | Operating range | 20 | |
| X, Y amplitude | AX, AY | 6000 | 9500 | 15781 | digits | At ambient temperature | 20 |
| X, Y amplitude | AX, AY | 3922 | 20620 | digits | Operating range | 20 | |
| X, Y synchronicity | k | 87.5 | 100 | 112.49 | % | 20 | |
| X, Y offset | OX, OY | -2048 | 0 | 2047 | digits | 20 | |
| X, Y orthogonality error | j | -11.25 | 0 | 11.24 | ° | 20 | |
| X, Y amplitude without magnet | X0, Y0 | 4096 | digits | Operating range | 20 | ||
| Overall angle error (without auto-calibration) | αErr | 1.9 | ° | Including lifetime and temperature drift | 21 | ||
| PWM output frequency 1 | fPWM1 | 232 | 244 | 262 | Hz | 33 | |
| PWM output frequency 2 | fPWM2 | 464 | 488 | 525 | Hz | 33 | |
| PWM output frequency 3 | fPWM3 | 929 | 977 | 1050 | Hz | 33 | |
| PWM output frequency 4 | fPWM4 | 1855 | 1953 | 2099 | Hz | 33 | |
| Output duty cycle range | DYPWM | 6.25 | 93.75 | % | Absolute angle | 33 | |
| Thermal resistance junction to air | RthJA | 150 | 200 | K/W | Junction to air, according to Jedec JESD51-7 | 47 | |
| Thermal resistance junction to case | RthJC | 75 | K/W | Junction to case | 47 | ||
| Thermal resistance junction to lead | RthJL | 85 | K/W | Junction to lead | 47 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Lead Frame Cu Plating Sn 100% > 7 µm | 47 |
CAD (KiCad official)
- Symbol:
TLE5012BE1000XUMA1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tle5012be1000xuma1-etched.step/tle5012be1000xuma1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tle5012be1000xuma1.step/tle5012be1000xuma1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (51 pp, sha256
9c7f6b6671373462, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).