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CS1259B-SOP16
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CHIPSEA Analog To Digital Converters (ADC), SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCS1259B-SOP16
CHIPSEA · Analog To Digital Converters (ADC) · SOP-16
CS1259B-SOP16 from CHIPSEA, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REFN | input | Negative reference voltage input; for single-ended measurements it should be connected to GND. |
| 2 | AIN0 | input | Analog signal input channel 0, usable single-ended against REFN or combined with another AINx into a differential pair. |
| 3 | AIN1 | input | Analog signal input channel 1, usable single-ended against REFN or combined with another AINx into a differential pair. |
| 4 | CIP | bidirectional | Positive terminal of the analog signal filter port, used to connect an external RC filter when EXFIL_EN is enabled. |
| 5 | CIN | bidirectional | Negative terminal of the analog signal filter port, used to connect an external RC filter when EXFIL_EN is enabled. |
| 6 | AIN4 | input | Analog signal input channel 4, usable single-ended against REFN or combined with another AINx into a differential pair. |
| 7 | AIN3 | input | Analog signal input channel 3, usable single-ended against REFN or combined with another AINx into a differential pair. |
| 8 | AIN2 | input | Analog signal input channel 2, usable single-ended against REFN or combined with another AINx into a differential pair. |
| 9 | CS | input | Serial interface chip-select, active low; the pin is internally floating so an external pull-up is recommended. |
| 10 | SCLK | input | Serial communication clock input; SDA data is shifted out on the rising edge and sampled on the falling edge of SCLK. |
| 11 | SDA | bidirectional | Serial data input/output; when CS is high it outputs DRDY to flag conversion data ready, and when CS is low it carries serial communication data. |
| 12 | GND | power_in | Ground. |
| 13 | VDD | power_in | Supply voltage, 2.4 V to 3.6 V (3.0 V typical) per the electrical characteristics; absolute maximum is -0.3 V to 6 V. |
| 14 | GND | power_in | Ground. |
| 15 | VS | power_in | Internal LDO output that powers the external bridge sensor and internal ADC, selectable via LDOS[1:0] and rated for a load current up to 10 mA. |
| 16 | REFP | input | Positive reference voltage input; the ADC reference is REFP minus REFN, with REFP specified from VS/2 to VDD+0.1 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CHIPSEA |
| Package | SOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog supply voltage | VDD | -0.3 | 6 | V | VDD to GND | 8 | |
| Supply momentary input current | 100 | mA | Input Current momentary | 8 | |||
| Supply continuous input current | 10 | mA | Input Current continuous | 8 | |||
| Digital input voltage to GND | -0.3 | V | Max printed as VDD+0.3 (not numeric) | 9 | |||
| Digital output voltage to GND | -0.3 | V | Max printed as VDD+0.3 (not numeric) | 9 | |||
| Maximum junction temperature | 150 | ℃ | 9 | ||||
| Operating temperature | -40 | 85 | ℃ | 9 | |||
| Storage temperature | -60 | 150 | ℃ | 9 | |||
| Lead temperature (soldering) | 300 | ℃ | Soldering, 10s | 9 | |||
| Supply voltage | VDD | 2.4 | 3 | 3.6 | V | 10 | |
| Operating temperature | -40 | 85 | ℃ | Stated in section 1.5 text | 9 | ||
| Data rate | 10 | 40 | 1280 | SPS | 9 | ||
| Offset error, Gain=128 | -8 | 8 | uV | Gain=128 | 9 | ||
| Offset error, Gain=1 | -100 | 100 | uV | Gain=1 | 9 | ||
| Offset error drift, Gain=128 | -0.5 | 0.5 | nv/℃ | Gain=128 | 9 | ||
| Gain error, Gain=128 | -5 | 5 | % | Gain=128 | 9 | ||
| Gain error, Gain=1 | -1 | 1 | % | Gain=1 | 9 | ||
| VS voltage | VS | 2.32 | 2.35 | 2.38 | V | LDOS[1:0]=00 | 9 |
| VREF voltage | VREF | 1.212 | 1.225 | 1.238 | V | 9 | |
| Supply/timing t3: SCLK low before CS falling | t3 | 5 | ns | 26 | |||
| SCLK low after CS rising | t4 | 5 | ns | 26 | |||
| SDA data setup before SCLK rising | t5 | 5 | ns | 26 | |||
| SDO stable after SCLK rising | t7 | 50 | ns | 26 | |||
| SCLK high width | t8 | 170 | us | Min printed as 2*sysclk (not numeric) | 26 | ||
| SCLK low width | t9 | 680 | us | Min printed as 2*sysclk (not numeric) | 26 | ||
| Power down current, ADC | 0.1 | 1 | uA | Power down | 10 | ||
| Power down current, digital | 0.2 | 1.3 | uA | Power down | 10 | ||
| Differential input impedance | 100 | MΩ | PGA Buffer on | 9 | |||
| Resolution | 24 | Bits | No missing codes | 9 | |||
| Settling time | 4 | 转换周期 | 9 | ||||
| Noise, Gain=32×2 | 95 | nV | Gain=32×2, 160Hz | 9 | |||
| Noise, Gain=1×1 | 2.3 | uV | Gain=1×1, 160Hz | 9 | |||
| Integral linearity | 0.0015 | % of FS | Gain=128 | 9 | |||
| Offset error drift, Gain=1 | 0.4 | uv/℃ | Gain=1 | 9 | |||
| Gain error drift, Gain=128 | 8 | ppm/℃ | Gain=128 | 9 | |||
| VS temperature drift | VS | 30 | ppm/℃ | 9 | |||
| VREF temperature drift | VREF | 30 | ppm/℃ | 9 | |||
| Clock frequency | 5.898 | MHz | 10 | ||||
| Clock trim accuracy | 1 | % | trim精度 | 10 | |||
| Clock frequency variation over temperature | 2 | % | 全温度变化 | 10 | |||
| Clock frequency variation over supply voltage | 1 | % | 全电压变化 | 10 | |||
| Input high leakage current | IIH | 1 | uA | VI=VDD | 10 | ||
| Input low leakage current | IIL | -1 | uA | VI=GND | 10 | ||
| ADC operating current, normal mode | 0.6 | mA | 普通模式 | 10 | |||
| ADC operating current, performance mode | 1.1 | mA | 性能模式 | 10 | |||
| LDO operating current | 160 | uA | 10 | ||||
| VREF operating current, temperature compensation started | 280 | uA | 启动温度补偿 | 10 | |||
| VREF operating current, temperature compensation not started | 210 | uA | 不启动温度补偿 | 10 | |||
| OSC operating current | 78 | uA | Freq=5.898MHz | 10 | |||
| Digital operating current | 230 | uA | 正常工作 | 10 | |||
| Overall current, ADC+LDO+digital, normal mode | 1 | mA | ADC普通模式 | 10 | |||
| Overall current, ADC+LDO+digital, performance mode | 1.5 | mA | ADC性能模式 | 10 | |||
| Overall current, ADC+LDO+digital, duty-cycle mode | 0.4 | mA | ADC占空比模式 | 10 |
CAD (KiCad official)
- Symbol:
CS1259B-SOP16 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
cs1259b-sop16-etched.step/cs1259b-sop16-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cs1259b-sop16.step/cs1259b-sop16.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: CHIPSEA datasheet (27 pp, sha256
a9156f9ac81c75f4, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).