TPS2492PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	UVEN	input	A low input inhibits GATE, and a logic input can drive this pin as an enable; the GATE driver is enabled only after the positive UVEN threshold is exceeded.
2	VREF	power_in	VREF is a 4-V reference voltage used to set the power threshold on PROG and is limited to 1 mA of sourcing current.
3	PROG	input	PROG is the FET power-limit programming pin, with a 0.4-V minimum applied voltage and no voltages above 4 V permitted.
4	TIMER	bidirectional	A capacitor from TIMER to ground sets the fault timer period, and the pin should be tied to ground if the timer feature is not used.
5	OV	input	OV is the overvoltage sensing input, and a high input inhibits GATE.
6	IMON	output	IMON is the current monitor output, nominally VIMON = 48 x (VVCC-SENSE), with 1.9 mA maximum sourcing current.
7	GND	power_in	GND is the ground reference pin for the device.
8	PG	output	PG is the active-low power good output, driven by VVCC-SENSE, and is an open-drain output while UVLO or POR is active.
9	FLT	output	FLT is the active-low fault indicator output that indicates the fault timer has expired and is reset by UVEN, UVLO, or automatic restart.
10	NC	unconnected	NC is a no-connect pin with no internal connection.
11	OUT	input	OUT is the FET source voltage sensing pin, and the gate is clamped to a diode drop below OUT; a clamp diode is recommended if the load can drive OUT below ground, clamping above -1 V.
12	GATE	output	GATE is the high-side gate driver output for the external N-channel FET, with a 22-µA pull-up and 125-mA strong pull-down.
13	SENSE	input	SENSE monitors the FET drain voltage and the downstream side of RSENSE, with current sensed as VVCC-SENSE and the current limit clamped to 50 mV at low FET VDS.
14	VCC	power_in	VCC is the input supply and current sense positive input, with a supply operating range of 9 V to 80 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-14
Category	Power Management (PMIC)
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage input range	VCC	9		80	V		2
Junction operating temperature	TJ	-40		125	°C		2
PROG input voltage	VPROG	0.4		4	V		2
VREF sourcing current	IVREF	0	1	1	mA		2
VREF capacitive loading	CVREF	0		1000	pF		2
Input voltage VCC SENSE UVEN OUT	VCC	-0.3		100	V	with respect to GND	2
Input voltage PROG OV	VPROG_OV	-0.3		6	V	with respect to GND	2
VCC - SENSE differential voltage	VCC-SENSE	-1.5		1.5	V		2
Output voltage GATE PG FLT	VOUT	-0.3		100	V	with respect to GND	2
Output voltage TIMER VREF IMON	VOUT	-0.3		6	V	with respect to GND	2
PG FLT sink current	ISINK			10	mA		2
PROG sink current				2	mA		2
VREF source current				2	mA		2
ESD HBM rating				2	kV	HBM	2
Junction-to-ambient thermal resistance	θJA		116.4		°C/W		2
Junction-to-board thermal resistance	θJB		53.8		°C/W		2
Input UVLO VCC turn-on rising	VVCC		8.4	8.8	V	Rising	3
UVLO hysteresis		50	100	150	mV		3
Supply current enabled	IVCC		665	1000	µA	VUVEN = Hi, VSENSE = VOUT = VVCC	3
Supply current disabled	IVCC		120	250	µA	VUVEN = Lo, VSENSE = VVCC, VOUT = 0	3
SENSE input bias current	ISENSE		7.5	20	µA	VSENSE = VOUT = VVCC	3
Reference voltage	VREF	3.9	4	4.1	V	0 ≤ IVREF ≤ 1 mA	3
PROG input bias current	IPROG		5		µA	0.4 ≤ VPROG ≤ 4 V, VUVEN = 48 V	3
PROG pull down resistance	RPROG	375		600	Ω	IPROG = 200 µA; VUVEN = 0 V	3
Current limit threshold with power limiting trip	V(VCC-SENSE)	17	25	33	mV	VPROG = 2.4 V; VOUT = 0 V; VVCC = 48 V	3
Current limit threshold without power limiting trip	V(VCC-SENSE)	45	50	55	mV	VPROG = 4 V; VSENSE = VOUT	3
TIMER source current	ISOURCE	17	27	36	µA	VTIMER = 0 V	3
TIMER sink current	ISINK	1.5	2.7	3.7	µA	VTIMER = 5 V	3
TIMER upper threshold	VTIMER	3.9	4	4.1	V		3
TIMER lower reset threshold	VTIMER	0.96	1	1.04	V	TPS2492 only	3
FLT low voltage sinking	V		0.1	0.25	V	IFLT = 2 mA	3
FLT low voltage sinking	V		0.25	0.5	V	IFLT = 4 mA	3
FLT leakage current	ILEAKAGE			10	µA	FLT high impedance	3
UVEN threshold voltage rising	VUVEN_H	1.31	1.35	1.39	V	UVEN rising	3
UVEN hysteresis		80	100	120	mV		3
UVEN leakage current				1	µA	VUVEN = 48 V	3
GATE sourcing current		15	22	35	µA	VSENSE = VVCC; V(GATE-OUT) = 7 V; VUVEN = Hi	4
GATE sinking current	IGATE	1.8	2.4	2.8	mA	VUVEN = Lo; VGATE = VVCC	4
GATE strong pull down sinking current	IGATE	75	125	250	mA	UVEN = Hi; VGATE = VVCC; VVCC - VSENSE = 200 mV	4
GATE output voltage VGATE - VOUT	VGATE		12	16	V	VUVEN = Hi, VCC = SENSE = OUT, measure VGATE - VOUT	4
Propagation delay UVEN high to GATE output high	tD_ON		25	40	µs	VUVEN = 0 → 2.5 V; 50% of VUVEN to 50% of VGATE; VOUT = VVCC; R(GATE-OUT) = 1 MΩ	4
Propagation delay UVEN low to GATE output low	tD_OFF		0.5	1	µs	VUVEN = 2.5 V → 0 V; 50% of VUVEN to 50% of VGATE; VOUT = VVCC; R(GATE-OUT) = 1 MΩ; tFALL < 0.1 µs	4
Propagation delay TIMER expires to GATE output low	tD_FAULT		0.8	1	µs	VTIMER: 0 → 5 V; tRISE < 0.1 µs; 50% of VTIMER to 50% of VGATE; VOUT = VCC; R(GATE-OUT) = 1 MΩ	4
PG low voltage sinking	V		0.1	0.25	V	IPG = 2 mA	4
PG low voltage sinking	V		0.25	0.5	V	IPG = 4 mA	4
PG threshold voltage PG goes low	V(VCC-OUT)	0.8	1.25	1.7	V	VOUT rising; VSENSE = VVCC	4
PG threshold voltage PG goes open drain	V(VCC-OUT)	2.2	2.7	3.2	V	VOUT falling; VSENSE = VVCC	4
PG threshold hysteresis voltage	V(SENSE-OUT)		1.4		V	VSENSE = VVCC	4
PG deglitch delay	tDPG	5	9	15	ms	VSENSE = VVCC; rising and falling edges	4
PG leakage current	ILEAKAGE			10	µA	PG false open drain	4
OV threshold voltage rising	VOV_H	1.31	1.35	1.39	V	OV rising	4
OV hysteresis		70	90	110	mV		4
OV leakage current sinking	ILEAKAGE			1	µA	VOV = 5 V	4
Maximum duration of OV strong gate pull down		40	100	220	µs		4
OUT bias current sinking	IOUT		8	20	µA	VOUT = VVCC, VUVEN = Hi	4
OUT bias current sourcing	IOUT		18	40	µA	VOUT = GND; VUVEN = Lo	4
IMON maximum output voltage		2.6	2.8	3	V	VCC - VSENSE = 200 mV	4
IMON gain V(IMON)/V(VCC-SENSE)		46	48	50	V/V		4
IMON offset voltage	VOFFSET	-50	-5	30	mV		4
IMON source current	ISOURCE		1.9		mA		4
IMON sink current	ISINK		60		µA		4
Junction-to-board characterization parameter	ψJB		58.8		°C/W		2

CAD (KiCad official)

Symbol: TPS2492PWR
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: tps2492pwr-etched.step / tps2492pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps2492pwr.step / tps2492pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (36 pp, sha256 5a3953974c9098a7, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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TPS2492PWR

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