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AT45DB081E-SSHN-T

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Dialog Semiconductor Adesto Adesto Technologies NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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AT45DB081E-SSHN-T

Dialog Semiconductor Adesto Adesto Technologies · NOR FLASH · SOIC-8

AT45DB081E-SSHN-T from Dialog Semiconductor Adesto Adesto Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SI input Serial Input shifts in all command, address and data, latched on the rising edge of SCK and ignored when the device is deselected.
2 SCK input Serial Clock controls data flow to and from the device; input is latched on the rising edge and output is clocked out on the falling edge of SCK.
3 RESET input Active-low reset terminates the operation in progress and resets the internal state machine to idle; drive high externally if unused.
4 CS input Active-low Chip Select selects the device; when deasserted the device is deselected, normally enters standby, and SO goes high-impedance.
5 WP input Active-low Write Protect protects all sectors set in the Sector Protection Register against program and erase; internally pulled high, may be left floating but connecting to VCC is recommended.
6 VCC power_in Device power supply (1.7V to 3.6V); operation at invalid VCC voltages may produce spurious results.
7 GND power_in Ground reference for the power supply, to be connected to system ground.
8 SO tri_state Serial Output shifts data out on the falling edge of SCK and is high-impedance whenever the device is deselected.

Key specifications

Parameter Value
Manufacturer Dialog Semiconductor Adesto Adesto Technologies
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ultra-Deep Power-Down Current IUDPD 0.4 1 µA CS= VCC. All other inputs at 0V or VCC 47
Deep Power-Down Current IDPD 4.5 12 µA CS= VCC. All other inputs at 0V or VCC 47
Standby Current ISB 25 40 µA CS= VCC. All other inputs at 0V or VCC 47
Active Current, Low Power Read (01h) ICC1 6 9 mA f = 1MHz; IOUT = 0mA 47
Active Current, Low Power Read (01h) ICC1 7 10 mA f = 15MHz; IOUT = 0mA 47
Active Current, Read Operation ICC2 10 12 mA f = 50MHz; IOUT = 0mA 47
Active Current, Read Operation ICC2 12 15 mA f = 85MHz; IOUT = 0mA 47
Active Current, Program Operation ICC3 14 16 mA CS = VCC 47
Active Current, Erase Operation ICC4 8 12 mA CS = VCC 47
Input Load Current ILI 1 µA All inputs at CMOS levels 47
Output Leakage Current ILO 1 µA All inputs at CMOS levels 47
Input Low Voltage VIL 0.3 x VCC 47
Input High Voltage VIH 0.7 x VCC 47
Input High Voltage (upper limit) VIH 0.6 V (VCC + offset) 47
Output Low Voltage VOL 0.4 V IOL = 100µA 47
Output High Voltage VOH -0.2 V (VCC + offset) IOH = -100µA 47
SCK Frequency fSCK 85 MHz 1.7V to 3.6V range 48
SCK Frequency for Continuous Read (0x0B) fCAR1 85 MHz 1.7V to 3.6V range 48
SCK Frequency for Continuous Read (0x03) (Low Frequency) fCAR2 50 MHz 1.7V to 3.6V range 48
SCK Frequency for Continuous Read (Low Power Mode, 01h Opcode) fCAR3 20 MHz 1.7V to 3.6V range 48
SCK Frequency for Continuous Read (0x1B) fCAR4 85 MHz 1.7V to 3.6V range 48
SCK High Time tWH 4 ns 48
SCK Low Time tWL 4 ns 48
SCK Rise Time, Peak-to-peak tSCKR 0.1 V/ns 48
SCK Fall Time, Peak-to-peak tSCKF 0.1 V/ns 48
Minimum CS High Time tCS 30 ns 48
CS Setup Time tCSS 6 ns 1.7V to 3.6V range 48
CS Hold Time tCSH 5 ns 1.7V to 3.6V range 48
Data In Setup Time tSU 2 ns 48
Data In Hold Time tH 1 ns 48
Output Hold Time tHO 0 ns 48
Output Disable Time tDIS 8 ns 1.7V to 3.6V range 48
Output Valid tV 7 ns 1.7V to 3.6V range 48
WP Low to Protection Enabled tWPE 1 µs 48
WP High to Protection Disabled tWPD 1 µs 48
Freeze Sector Lockdown Time (from CS High) tLOCK 200 µs from CS High 48
CS High to Ultra-Deep Power-Down tEUDPD 3 µs 48
Minimum CS Low Time to Exit Ultra-Deep Power-Down tCSLU 20 ns 48
Exit Ultra-Deep Power-Down Time tXUDPD 100 µs 48
CS High to Deep Power-Down tEDPD 3 µs 48
Resume from Deep Power-Down Time tRDPD 35 µs 48
RESET Pulse Width tRST 10 µs 48
RESET Recovery Time tREC 1 µs 48
Software Reset Time tSWRST 50 µs 48
Page Erase and Programming Time (256/264 bytes) tEP 15 55 ms 1.7V to 3.6V range 49
Page Programming Time tP 2 4 ms 1.7V to 3.6V range 49
Byte Programming Time tBP 8 µs 1.7V to 3.6V range 49
Page Erase Time tPE 12 50 ms 1.7V to 3.6V range 49
Block Erase Time tBE 30 75 ms 1.7V to 3.6V range 49
Sector Erase Time tSE 0.7 1.3 s 1.7V to 3.6V range 49
Chip Erase Time tCE 10 20 s 1.7V to 3.6V range 49
Suspend Time (Program) tSUSP 10 20 µs Program 49
Resume Time (Program) tRES 3 5 µs Program 49
Temperature Under Bias -55 125 C 46
Storage Temperature -65 150 C 46
All Input Voltages (except VCC, including NC pins) with respect to Ground -0.6 0.6 V (VCC + offset) 46
All Output Voltages with respect to Ground -0.6 0.6 V (VCC + offset) 46
Operating Temperature (Case) Industrial -40 85 C 46
VCC Power Supply VCC 1.7 3.6 V 46

CAD (KiCad official)

  • Symbol: AT45DB081E-SSHN-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at45db081e-sshn-t-etched.step / at45db081e-sshn-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at45db081e-sshn-t.step / at45db081e-sshn-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Dialog Semiconductor Adesto Adesto Technologies datasheet (70 pp, sha256 e216291379cff608, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF