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Contents

README

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SSM6J808R

TOSHIBA · MOSFETs · TSOP-6

SSM6J808R from TOSHIBA, in a TSOP-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Drain passive Drain terminal of the P-channel MOSFET; the absolute maximum drain-source voltage VDSS is -40 V and the DC drain current ID is -7 A.
2 Drain passive Drain terminal of the P-channel MOSFET; the absolute maximum drain-source voltage VDSS is -40 V and the DC drain current ID is -7 A.
3 Gate input Gate terminal of the P-channel MOSFET; the absolute maximum gate-source voltage VGSS is -20/+10 V.
4 Source passive Source terminal of the P-channel MOSFET; the datasheet gives the ratings (VDSS, VGSS) referenced to this terminal and specifies no separate source limit.
5 Drain passive Drain terminal of the P-channel MOSFET; the absolute maximum drain-source voltage VDSS is -40 V and the DC drain current ID is -7 A.
6 Drain passive Drain terminal of the P-channel MOSFET; the absolute maximum drain-source voltage VDSS is -40 V and the DC drain current ID is -7 A.

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package TSOP-6
Category Transistors/Thyristors
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source voltage VDSS -40 V Ta = 25 °C, as printed in Absolute Maximum Ratings 2
Gate-source voltage VGSS -20 10 V Printed as -20/+10 2
Drain current (DC) ID -7 A 2
Drain current (pulsed) IDP -35 A Pulse width (PW) ≤ 10 µs, duty ≤ 1 % (Note 2) 2
Power dissipation PD 1.53 W Device mounted on 25.4 mm × 25.4 mm × 1.6 mm FR4 board, Cu pad 645 mm² (Note 3) 2
Channel temperature Tch 150 °C 2
Storage temperature Tstg -55 150 °C 2
Single-pulse avalanche energy EAS 40 mJ VDD = -32 V, Tch = 25 °C (initial state), L = 1 mH, RG = 25 Ω (Note 4) 2
Single-pulse avalanche current IAS -6.3 A 2
Gate leakage current IGSS -100 100 nA VDS = 0 V, VGS = -20/+10 V 3
Drain cut-off current IDSS -10 µA VDS = -40 V, VGS = 0 V 3
Drain-source breakdown voltage V(BR)DSS -40 V ID = -10 mA, VGS = 0 V 3
Drain-source breakdown voltage (VGS applied) V(BR)DSX -30 V ID = -10 mA, VGS = 10 V 3
Gate threshold voltage Vth -0.8 -2 V VDS = -10 V, ID = -0.1 mA 3
Drain-source on-resistance RDS(ON) 38 52 mΩ ID = -2.5 A, VGS = -4 V 3
Drain-source on-resistance RDS(ON) 35 48 mΩ ID = -2.5 A, VGS = -4.5 V 3
Drain-source on-resistance RDS(ON) 28 35 mΩ ID = -2.5 A, VGS = -10 V 3
Diode forward voltage VDSF 0.86 1.2 V ID = 7 A, VGS = 0 V 3

CAD (KiCad official)

  • Symbol: SSM6J808R
  • Footprint: Package_SO:TSOP-6_1.65x3.05mm_P0.95mm
  • 3D model: TSOP-6 (KiCad packages3D, STEP)
  • 3D model files: ssm6j808r-etched.step / ssm6j808r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ssm6j808r.step / ssm6j808r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (9 pp, sha256 5197fedef8f7fbe6, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF