component
CA-IS3741LW
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCA-IS3741LW
Chipanalog · Digital Isolators · SOIC-16-300mil
CA-IS3741LW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | A-side power supply, operating from 2.375 V to 5.5 V (recommended), with a 0.1 µF to 1 µF bypass capacitor required. |
| 2 | GNDA | power_in | A-side ground reference for the isolated input-side circuitry. |
| 3 | VI1 | input | A-side logic input for forward channel 1, TTL-compatible with Schmitt-trigger input (VIH 2.0 V min, VIL 0.8 V max). |
| 4 | VI2 | input | A-side logic input for forward channel 2, TTL-compatible with Schmitt-trigger input (VIH 2.0 V min, VIL 0.8 V max). |
| 5 | VI3 | input | A-side logic input for forward channel 3, TTL-compatible with Schmitt-trigger input (VIH 2.0 V min, VIL 0.8 V max). |
| 6 | VO4 | output | A-side logic output of the reverse channel 4 (driven from B-side input VI4), which goes high-impedance when ENA is low. |
| 7 | ENA | input | A-side output enable, active high, internally pulled up to local VDD; if left floating keep traces off this pin, and drive it to a defined logic level in noisy environments. |
| 8 | GNDA | power_in | A-side ground reference for the isolated input-side circuitry. |
| 9 | GNDB | power_in | B-side ground reference for the isolated output-side circuitry. |
| 10 | ENB | input | B-side output enable, active high, internally pulled up to local VDD; if left floating keep traces off this pin, and drive it to a defined logic level in noisy environments. |
| 11 | VI4 | input | B-side logic input for reverse channel 4 (drives A-side output VO4), TTL-compatible with Schmitt-trigger input. |
| 12 | VO3 | output | B-side logic output of forward channel 3, which goes high-impedance when ENB is low. |
| 13 | VO2 | output | B-side logic output of forward channel 2, which goes high-impedance when ENB is low. |
| 14 | VO1 | output | B-side logic output of forward channel 1, which goes high-impedance when ENB is low. |
| 15 | GNDB | power_in | B-side ground reference for the isolated output-side circuitry. |
| 16 | VDDB | power_in | B-side power supply, operating from 2.375 V to 5.5 V (recommended), with a 0.1 µF to 1 µF bypass capacitor required. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16-300mil |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDDA, VDDB | VDDA, VDDB | -0.5 | 7 | V | Referenced to local GND (GNDA or GNDB); peak value (note 2) | 5 | |
| Input voltage Ax, Bx, ENx | Vin | -0.5 | V | Max printed as VDD+0.5; must not exceed 7 V (note 3) | 5 | ||
| Output current | IO | -20 | 20 | mA | 5 | ||
| Junction temperature | TJ | 150 | °C | 5 | |||
| Storage temperature range | TSTG | -65 | 150 | °C | 5 | ||
| Supply voltage | VDDA, VDDB | 2.375 | 5.5 | V | Typical printed as 3.3/5.0 V | 5 | |
| UVLO threshold, rising VDD | VDD(UVLO+) | 1.95 | 2.24 | 2.37 | V | VDD rising | 5 |
| UVLO threshold, falling VDD | VDD(UVLO-) | 1.88 | 2.1 | 2.325 | V | VDD falling | 5 |
| UVLO hysteresis | VHYS(UVLO) | 70 | 140 | 250 | mV | 5 | |
| High-level output current | IOH | -4 | mA | VDDO = 5 V | 5 | ||
| High-level output current | IOH | -2 | mA | VDDO = 3.3 V | 5 | ||
| High-level output current | IOH | -1 | mA | VDDO = 2.5 V | 5 | ||
| Low-level output current | IOL | 4 | mA | VDDO = 5 V | 5 | ||
| Low-level output current | IOL | 2 | mA | VDDO = 3.3 V | 5 | ||
| Low-level output current | IOL | 1 | mA | VDDO = 2.5 V | 5 | ||
| Input threshold logic high | VIH | 2 | V | 5 | |||
| Input threshold logic low | VIL | 0.8 | V | 5 | |||
| Signal data rate | DR | 0 | 150 | Mbps | 5 | ||
| Ambient temperature | TA | -40 | 27 | 125 | °C | 5 | |
| Output voltage logic low | VOL | 0.2 | 0.4 | V | VDDA = VDDB = 5 V ±10%, TA = -40 to 125°C; IOL = 4mA; 图 8-2 | 9 | |
| Input threshold logic high | VIT+(IN) | 2 | V | VDDA = VDDB = 5 V ±10%, TA = -40 to 125°C | 9 | ||
| Input threshold logic low | VIT-(IN) | 0.8 | V | VDDA = VDDB = 5 V ±10%, TA = -40 to 125°C | 9 | ||
| Input high-level leakage current | IIH | 20 | µA | VIH = VDDA at Ax, Bx or ENx; VDDA = VDDB = 5 V ±10% | 9 | ||
| Input low-level leakage current | IIL | -20 | µA | VIL = 0 V at Ax, Bx or ENx; VDDA = VDDB = 5 V ±10% | 9 | ||
| Common-mode transient immunity | CMTI | 100 | 150 | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-4; VDDA = VDDB = 5 V ±10% | 9 | |
| Supply current IDDA, DC signal (CA-IS3741L, input low) | IDDA | 1.6 | 2.5 | mA | VDDA = VDDB = 5 V ±10%; ENA = ENB = VDDI; VIN = 0V (CA-IS3741L) | 10 | |
| Supply current IDDB, DC signal (CA-IS3741L, input low) | IDDB | 2.5 | 3.9 | mA | VDDA = VDDB = 5 V ±10%; ENA = ENB = VDDI; VIN = 0V (CA-IS3741L) | 10 | |
| Supply current IDDA, DC signal (CA-IS3741L, input high) | IDDA | 4.2 | 6.9 | mA | VDDA = VDDB = 5 V ±10%; ENA = ENB = VDDI; VIN = VDDI (CA-IS3741L) | 10 | |
| Supply current IDDB, DC signal (CA-IS3741L, input high) | IDDB | 3.5 | 5.4 | mA | VDDA = VDDB = 5 V ±10%; ENA = ENB = VDDI; VIN = VDDI (CA-IS3741L) | 10 | |
| Supply current IDDA, 100 Mbps | IDDA | 14.3 | 19.8 | mA | VDDA = VDDB = 5 V ±10%; ENA = ENB = VDDI; all inputs 50% duty square wave 5 V; CL = 15 pF; 100Mbps (50MHz) | 10 | |
| Supply current IDDB, 100 Mbps | IDDB | 32.5 | 44 | mA | VDDA = VDDB = 5 V ±10%; ENA = ENB = VDDI; all inputs 50% duty square wave 5 V; CL = 15 pF; 100Mbps (50MHz) | 10 | |
| Supply current IDDA, DC signal (CA-IS3741L, input low) | IDDA | 1.5 | 2.4 | mA | VDDA = VDDB = 3.3 V ±10%; ENA = ENB = VDDI; VIN = 0V (CA-IS3741L) | 11 | |
| Supply current IDDB, DC signal (CA-IS3741L, input low) | IDDB | 2.4 | 3.7 | mA | VDDA = VDDB = 3.3 V ±10%; ENA = ENB = VDDI; VIN = 0V (CA-IS3741L) | 11 | |
| Supply current IDDA, DC signal (CA-IS3741L, input high) | IDDA | 4.1 | 6.8 | mA | VDDA = VDDB = 3.3 V ±10%; ENA = ENB = VDDI; VIN = VDDI (CA-IS3741L) | 11 | |
| Supply current IDDB, DC signal (CA-IS3741L, input high) | IDDB | 3.3 | 5.2 | mA | VDDA = VDDB = 3.3 V ±10%; ENA = ENB = VDDI; VIN = VDDI (CA-IS3741L) | 11 | |
| Supply current IDDA, 100 Mbps | IDDA | 10.3 | 14.5 | mA | VDDA = VDDB = 3.3 V ±10%; ENA = ENB = VDDI; all inputs 50% duty square wave 3.3 V; CL = 15 pF; 100Mbps (50MHz) | 11 | |
| Supply current IDDB, 100 Mbps | IDDB | 21.9 | 29.7 | mA | VDDA = VDDB = 3.3 V ±10%; ENA = ENB = VDDI; all inputs 50% duty square wave 3.3 V; CL = 15 pF; 100Mbps (50MHz) | 11 | |
| Supply current IDDA, DC signal (CA-IS3741L, input low) | IDDA | 1.5 | 2.4 | mA | VDDA = VDDB = 2.5 V ±5%; ENA = ENB = VDDI; VIN = 0V (CA-IS3741L) | 12 | |
| Supply current IDDB, DC signal (CA-IS3741L, input low) | IDDB | 2.4 | 3.7 | mA | VDDA = VDDB = 2.5 V ±5%; ENA = ENB = VDDI; VIN = 0V (CA-IS3741L) | 12 | |
| Supply current IDDA, DC signal (CA-IS3741L, input high) | IDDA | 4 | 6.7 | mA | VDDA = VDDB = 2.5 V ±5%; ENA = ENB = VDDI; VIN = VDDI (CA-IS3741L) | 12 | |
| Supply current IDDB, DC signal (CA-IS3741L, input high) | IDDB | 3.3 | 5.1 | mA | VDDA = VDDB = 2.5 V ±5%; ENA = ENB = VDDI; VIN = VDDI (CA-IS3741L) | 12 | |
| Supply current IDDA, 100 Mbps | IDDA | 8.4 | 11.9 | mA | VDDA = VDDB = 2.5 V ±5%; ENA = ENB = VDDI; all inputs 50% duty square wave 2.5 V; CL = 15 pF; 100Mbps (50MHz) | 12 | |
| Supply current IDDB, 100 Mbps | IDDB | 16.7 | 22.9 | mA | VDDA = VDDB = 2.5 V ±5%; ENA = ENB = VDDI; all inputs 50% duty square wave 2.5 V; CL = 15 pF; 100Mbps (50MHz) | 12 | |
| Junction-to-ambient thermal resistance (SOIC16-WB) | RθJA | 83.4 | °C/W | SOIC16-WB (W) column | 6 |
CAD (KiCad official)
- Symbol:
CA-IS3741LW - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
ca-is3741lw-etched.step/ca-is3741lw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3741lw.step/ca-is3741lw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (25 pp, sha256
fd7bb5373a55db4c, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).