component
VNS1NV04PTR-E
Public Made by Adomby adom
STMicroelectronics Power Distribution Switches, SOIC-8. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownVNS1NV04PTR-E
STMicroelectronics · Power Distribution Switches · SOIC-8
VNS1NV04PTR-E from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | INPUT | input | Gate control input terminal; input threshold voltage 0.5 to 2.5 V (VDS=VIN, ID=1 mA), maximum input current ±20 mA, and supply current 100 to 150 µA (VDS=0 V, VIN=5 V). |
| 2 | DRAIN | power_out | Drain terminal (one of four) of integrated power MOSFET with internally-clamped overvoltage protection at 40-55 V and linear current limiting to 1.7 A typical. |
| 3 | DRAIN | power_out | Drain terminal (one of four) of integrated power MOSFET with internally-clamped overvoltage protection at 40-55 V and linear current limiting to 1.7 A typical. |
| 4 | DRAIN | power_out | Drain terminal (one of four) of integrated power MOSFET with internally-clamped overvoltage protection at 40-55 V and linear current limiting to 1.7 A typical. |
| 5 | DRAIN | power_out | Drain terminal (one of four) of integrated power MOSFET with internally-clamped overvoltage protection at 40-55 V and linear current limiting to 1.7 A typical. |
| 6 | SOURCE | power_in | Source/ground return terminal (one of three); provides current return path for drain current and internal circuit supply. |
| 7 | SOURCE | power_in | Source/ground return terminal (one of three); provides current return path for drain current and internal circuit supply. |
| 8 | SOURCE | power_in | Source/ground return terminal (one of three); provides current return path for drain current and internal circuit supply. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Minimum input series impedance | RIN MINn | 330 | 6 | ||||
| Input current | IINn | -20 | 20 | mA | 6 | ||
| Reverse DC output current | IRn | -3 | A | 6 | |||
| Electrostatic discharge | VESD1 | 4000 | V | R=1.5 K, C=100 pF | 6 | ||
| Electrostatic discharge on output pins only | VESD2 | 16500 | V | R=330, C=150 pF | 6 | ||
| Total dissipation | Ptot | 8.3 | W | Tc=25 °C | 6 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 6 | ||
| Thermal resistance junction-ambient (SO-8) | Rthj-amb | 65 | °C/W | Standard single-sided FR4 board with 50 mm2 Cu (at least 35 µm) connected to all DRAIN pins | 7 | ||
| Drain-source clamp voltage | VCLAMP | 40 | 45 | 55 | V | VIN=0 V; ID=0.5 A | 7 |
| Input threshold voltage | VINTH | 0.5 | 2.5 | V | VDS=VIN; ID=1 mA | 7 | |
| Supply current from input pin | IISS | 100 | 150 | µA | VDS=0 V; VIN=5 V | 7 | |
| Drain-source clamp threshold voltage | VCLTH | 36 | V | VIN=0 V; ID=2 mA | 7 | ||
| Input-source clamp voltage | VINCL | 6 | 6.8 | 8 | V | IIN=1 mA | 7 |
| Input-source clamp voltage | VINCL | -1 | -0.3 | V | IIN=-1 mA | 7 | |
| Zero input voltage drain current (VIN=0 V) | IDSS | 30 | µA | VDS=13 V; VIN=0 V; Tj=25 °C | 7 | ||
| Zero input voltage drain current (VIN=0 V) | IDSS | 75 | µA | VDS=25 V; VIN=0 V | 7 | ||
| Static drain-source on resistance | RDS(on) | 250 | mΩ | VIN=5 V; ID=0.5 A; Tj=25 °C | 7 | ||
| Static drain-source on resistance | RDS(on) | 500 | mΩ | VIN=5 V; ID=0.5 A | 7 | ||
| Forward transconductance | gfs | 2 | S | VDD=13 V; ID=0.5 A | 7 | ||
| Turn-on delay time | td(on) | 70 | 200 | ns | VDD=15 V; ID=0.5 A; Vgen=5 V; Rgen=RIN MIN=330 (see Figure 4) | 7 | |
| Rise time | tr | 170 | 500 | ns | VDD=15 V; ID=0.5 A; Vgen=5 V; Rgen=RIN MIN=330 (see Figure 4) | 7 | |
| Turn-off delay time | td(off) | 350 | 1000 | ns | VDD=15 V; ID=0.5 A; Vgen=5 V; Rgen=RIN MIN=330 (see Figure 4) | 7 | |
| Fall time | tf | 200 | 600 | ns | VDD=15 V; ID=0.5 A; Vgen=5 V; Rgen=RIN MIN=330 (see Figure 4) | 7 | |
| Turn-on delay time | td(on) | 0.25 | 1 | µs | VDD=15 V; ID=0.5 A; Vgen=5 V; Rgen=2.2 K (see Figure 4) | 8 | |
| Rise time | tr | 1.3 | 4 | µs | VDD=15 V; ID=0.5 A; Vgen=5 V; Rgen=2.2 K (see Figure 4) | 8 | |
| Turn-off delay time | td(off) | 1.8 | 5.5 | µs | VDD=15 V; ID=0.5 A; Vgen=5 V; Rgen=2.2 K (see Figure 4) | 8 | |
| Fall time | tf | 1.2 | 4 | µs | VDD=15 V; ID=0.5 A; Vgen=5 V; Rgen=2.2 K (see Figure 4) | 8 | |
| Forward on voltage | VSD | 0.8 | V | ISD=0.5 A; VIN=0 V | 8 | ||
| Drain current limit | Ilim | 1.7 | 3.5 | A | VIN=5 V; VDS=13 V | 8 | |
| Over temperature shutdown | Tjsh | 150 | 175 | 200 | °C | 8 | |
| Over temperature reset | Tjrs | 135 | °C | 8 | |||
| Fault sink current | Igf | 10 | 15 | 20 | mA | VIN=5 V; VDS=13 V; Tj=Tjsh | 8 |
| Single pulse avalanche energy | Eas | 55 | mJ | Starting Tj=25 °C; VDD=24 V; VIN=5 V; Rgen=RIN MIN=330; L=50 mH (see Figure 6 and Figure 8) | 8 | ||
| Output capacitance | COSS | 90 | pF | VDS=13 V; f=1 MHz; VIN=0 V | 7 | ||
| Turn-on current slope | (dI/dt)on | 5 | A/µs | VDD=15 V; ID=1.5 A; Vgen=5 V; Rgen=RIN MIN=330 | 8 | ||
| Total input charge | Qi | 5 | nC | VDD=12 V; ID=0.5 A; VIN=5 V; Igen=2.13 mA (see Figure 7) | 8 | ||
| Reverse recovery time | trr | 205 | ns | ISD=0.5 A; dI/dt=6 A/µs; VDD=30 V; L=200 µH (see Figure 5) | 8 | ||
| Reverse recovery charge | Qrr | 100 | nC | ISD=0.5 A; dI/dt=6 A/µs; VDD=30 V; L=200 µH (see Figure 5) | 8 | ||
| Reverse recovery current | IRRM | 0.7 | A | ISD=0.5 A; dI/dt=6 A/µs; VDD=30 V; L=200 µH (see Figure 5) | 8 | ||
| Step response current limit | tdlim | 2 | µs | VIN=5 V; VDS=13 V | 8 |
CAD (KiCad official)
- Symbol:
VNS1NV04PTR-E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
vns1nv04ptr-e-etched.step/vns1nv04ptr-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);vns1nv04ptr-e.step/vns1nv04ptr-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (28 pp, sha256
4221a12bb53b0977, retrieved 2026-10-21, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).