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ADC12040CIVY

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Texas Instruments Analog To Digital Converters (ADC), TQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ADC12040CIVY

Texas Instruments · Analog To Digital Converters (ADC) · TQFP-32(7x7)

ADC12040CIVY from Texas Instruments, in a TQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREF power_in Reference input, 2.0V nominal, to be bypassed to ground with a 0.1 µF monolithic capacitor and kept between 1.0V and 2.4V.
2 VIN+ power_in Non-inverting analog signal input; with a 2.0V reference the ground-referenced input is 2.0 VP-P centered on VCM.
3 VIN− power_in Inverting analog signal input; with a 2.0V reference the ground-referenced input is 2.0 VP-P centered on VCM, and it may be tied to VCM for single-ended use, though a differential input is required for best performance.
4 AGND power_in Ground return for the analog supply.
5 VA power_in Positive analog supply, to be connected to a quiet +5V source (VA range +4.75V to +5.25V) and bypassed with 0.1 µF and 10 µF capacitors within 1 cm of the pin.
6 VA power_in Positive analog supply, to be connected to a quiet +5V source (VA range +4.75V to +5.25V) and bypassed with 0.1 µF and 10 µF capacitors within 1 cm of the pin.
7 AGND power_in Ground return for the analog supply.
8 PD input Power-down input; when high the converter is in power-down mode (40 mW typical), and when low it is in active mode.
9 DGND power_in Ground return for the digital supply.
10 CLK input Digital clock input, sampled on the rising edge of CLK.
11 OE input Output enable; when low it enables the TRI-STATE data outputs, and when high the outputs are in a high-impedance state.
12 DGND power_in Ground return for the digital supply.
13 VD power_in Positive digital supply, to be connected to the same quiet +5V source as VA (range +4.75V to +5.25V) and bypassed with 0.1 µF and 10 µF capacitors within 1 cm of the pin.
14 D0 output Digital data output bit of the 12-bit offset binary result (D0 is the LSB); outputs are TTL/CMOS compatible. Pin-to-bit mapping assumed sequential, see review notes.
15 D1 output Digital data output bit of the 12-bit offset binary result; outputs are TTL/CMOS compatible. Pin-to-bit mapping assumed sequential, see review notes.
16 D2 output Digital data output bit of the 12-bit offset binary result; outputs are TTL/CMOS compatible. Pin-to-bit mapping assumed sequential, see review notes.
17 D3 output Digital data output bit of the 12-bit offset binary result; outputs are TTL/CMOS compatible. Pin-to-bit mapping assumed sequential, see review notes.
18 D4 output Digital data output bit of the 12-bit offset binary result; outputs are TTL/CMOS compatible. Pin-to-bit mapping assumed sequential, see review notes.
19 D5 output Digital data output bit of the 12-bit offset binary result; outputs are TTL/CMOS compatible. Pin-to-bit mapping assumed sequential, see review notes.
20 DR GND power_in Ground return for the digital supply of the output drivers; connect to system ground and not in close proximity to DGND or AGND.
21 VDR power_in Positive supply for the output drivers, +2.35V to +5V and never exceeding VD, bypassed to DR GND with 0.1 µF (and 10 µF tantalum if supplied separately from VA and VD).
22 D6 output Digital data output bit of the 12-bit offset binary result; outputs are TTL/CMOS compatible. Pin-to-bit mapping assumed sequential, see review notes.
23 D7 output Digital data output bit of the 12-bit offset binary result; outputs are TTL/CMOS compatible. Pin-to-bit mapping assumed sequential, see review notes.
24 D8 output Digital data output bit of the 12-bit offset binary result; outputs are TTL/CMOS compatible. Pin-to-bit mapping assumed sequential, see review notes.
25 D9 output Digital data output bit of the 12-bit offset binary result; outputs are TTL/CMOS compatible. Pin-to-bit mapping assumed sequential, see review notes.
26 D10 output Digital data output bit of the 12-bit offset binary result; outputs are TTL/CMOS compatible. Pin-to-bit mapping assumed sequential, see review notes.
27 D11 output Digital data output bit of the 12-bit offset binary result (D11 is the MSB); outputs are TTL/CMOS compatible. Pin-to-bit mapping assumed sequential, see review notes.
28 AGND power_in Ground return for the analog supply.
29 VA power_in Positive analog supply, to be connected to a quiet +5V source (VA range +4.75V to +5.25V) and bypassed with 0.1 µF and 10 µF capacitors within 1 cm of the pin.
30 VRN passive High-impedance reference bypass pin; connect a 0.1 µF capacitor to AGND and do not load this pin.
31 VRP passive High-impedance reference bypass pin; connect a 0.1 µF capacitor to AGND and do not load this pin.
32 VRM passive High-impedance reference bypass pin; connect a 0.1 µF capacitor to AGND and do not load this pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-32(7x7)
Category Data Acquisition
Pins 32

CAD (KiCad official)

  • Symbol: ADC12040CIVY
  • Footprint: Package_QFP:TQFP-32_7x7mm_P0.8mm
  • 3D model: TQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: adc12040civy-etched.step / adc12040civy-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adc12040civy.step / adc12040civy.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 9140dac24f903190, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF