component
MC33063AVDR2G
Public Made by Adomby adom
onsemi DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC33063AVDR2G
onsemi · DC-DC Converters · SOIC-8
MC33063AVDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Switch Collector | passive | Collector of the internal output switch transistor Q2, rated 40 V maximum (VC(switch)) with switch current up to 1.5 A. |
| 2 | Switch Emitter | passive | Emitter of the internal output switch, rated 40 V maximum (VE(switch)) with switch current up to 1.5 A. |
| 3 | Timing Capacitor | passive | Connection for the external timing capacitor CT that sets the oscillator frequency (33 kHz typical with CT = 1.0 nF). |
| 4 | GND | power_in | Ground pin of the device. |
| 5 | Comparator Inverting Input | input | Inverting input of the comparator, which compares against the 1.25 V reference threshold (1.225 V to 1.275 V at 25 °C) and is rated -0.3 to +40 V. |
| 6 | VCC | power_in | Positive supply pin, operating from 3.0 V to 40 V with a 40 V maximum rating. |
| 7 | Ipk Sense | input | Peak current sense input, where the current limit trips at about 300 mV (250 to 350 mV) across the sense resistor Rsc between VCC and this pin. |
| 8 | Driver Collector | passive | Collector of the internal driver transistor Q1, rated 40 V maximum with driver collector current up to 100 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Oscillator frequency | fosc | 24 | 33 | 42 | kHz | VPin 5 = 0 V, CT = 1.0 nF, TA = 25°C | 3 |
| Charge current | Ichg | 24 | 35 | 42 | A | VCC = 5.0 V to 40 V, TA = 25°C | 3 |
| Discharge current | Idischg | 140 | 220 | 260 | A | VCC = 5.0 V to 40 V, TA = 25°C | 3 |
| Discharge to charge current ratio | Idischg/Ichg | 5.2 | 6.5 | 7.5 | − | Pin 7 to VCC, TA = 25°C | 3 |
| Current limit sense voltage | Vipk(sense) | 250 | 300 | 350 | mV | Ichg = Idischg, TA = 25°C | 3 |
| Saturation voltage, Darlington connection | VCE(sat) | 1 | 1.3 | V | ISW = 1.0 A, Pins 1, 8 connected | 3 | |
| Saturation voltage, non-Darlington | VCE(sat) | 0.45 | 0.7 | V | ISW = 1.0 A, RPin 8 = 82 Ω to VCC, Forced [symbol not extracted] = 20 | 3 | |
| DC current gain | hFE | 50 | 75 | − | ISW = 1.0 A, VCE = 5.0 V, TA = 25°C | 3 | |
| Collector off-state current | IC(off) | 0.01 | 100 | A | VCE = 40 V | 3 | |
| Threshold voltage | Vth | 1.225 | 1.25 | 1.275 | V | TA = 25°C | 3 |
| Threshold voltage over temperature | Vth | 1.21 | 1.29 | V | TA = Tlow to Thigh [Note 4] | 3 | |
| Threshold voltage line regulation | Regline | 1.4 | 6 | mV | VCC = 3.0 V to 40 V; MC33063V, NCV33063 column | 3 | |
| Input bias current | IIB | -20 | -400 | nA | Vin = 0 V | 3 | |
| Supply current | ICC | 4 | mA | VCC = 5.0 V to 40 V, CT = 1.0 nF, Pin 7 = VCC, VPin 5 > Vth, Pin 2 = GND, remaining pins open | 3 | ||
| Power supply voltage | VCC | 40 | Vdc | 2 | |||
| Comparator input voltage range | VIR | -0.3 | 40 | Vdc | 2 | ||
| Switch collector voltage | VC(switch) | 40 | Vdc | 2 | |||
| Switch emitter voltage | VE(switch) | 40 | Vdc | VPin 1 = 40 V | 2 | ||
| Switch collector to emitter voltage | VCE(switch) | 40 | Vdc | 2 | |||
| Driver collector voltage | VC(driver) | 40 | Vdc | 2 | |||
| Driver collector current | IC(driver) | 100 | mA | See Note 1 | 2 | ||
| Switch current | ISW | 1.5 | A | 2 | |||
| Power dissipation, SOIC package | PD | 625 | mW | SOIC, D suffix, TA = 25°C | 2 | ||
| Thermal resistance junction-to-ambient, SOIC package | RθJA | 160 | °C/W | SOIC, D suffix | 2 | ||
| Thermal resistance junction-to-case, SOIC package | RθJC | 45 | °C/W | SOIC, D suffix | 2 | ||
| Operating junction temperature | TJ | 150 | °C | 2 | |||
| Operating ambient temperature range | TA | -40 | 125 | °C | MC33063AV, NCV33063A | 2 | |
| Storage temperature range | Tstg | -65 | 150 | °C | 2 | ||
| Operating input voltage (features) | VCC | 3 | 40 | V | Features list: operation from 3.0 V to 40 V input | 1 |
CAD (KiCad official)
- Symbol:
MC33063AVDR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mc33063avdr2g-etched.step/mc33063avdr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc33063avdr2g.step/mc33063avdr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (15 pp, sha256
457d21fce6f3fe98, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).