component
TLC271ACP
Public Made by Adomby adom
Texas Instruments Operational Amplifier, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLC271ACP
Texas Instruments · Operational Amplifier · PDIP-8
TLC271ACP from Texas Instruments, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OFFSET N1 | passive | Offset-null terminal of the amplifier; the datasheet labels this pin but states no further function or electrical limit for it. |
| 2 | IN- | input | Inverting input; for C-suffix and I-suffix types the common-mode input voltage range extends below the negative rail. |
| 3 | IN+ | input | Non-inverting input; for C-suffix and I-suffix types the common-mode input voltage range extends below the negative rail. |
| 4 | GND | power_in | Negative supply rail (ground) for single-supply operation; the output voltage range includes this negative rail. |
| 5 | OFFSET N2 | passive | Offset-null terminal of the amplifier; the datasheet labels this pin but states no further function or electrical limit for it. |
| 6 | OUT | output | Amplifier output whose voltage range includes the negative rail; the inputs and output are designed to withstand -100 mA surge currents without latch-up. |
| 7 | VDD | power_in | Positive supply; for the C-suffix (0°C to 70°C) devices such as TLC271ACP the supply range is 3 V to 16 V. |
| 8 | BIAS SELECT | input | Selects high, medium, or low bias mode, trading ac performance (e.g., slew rate 3.6 V/µs high vs 0.03 V/µs low) against power dissipation (3375 µW high vs 50 µW low at VDD = 5 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-8 |
| Category | Amplifiers/Comparators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input offset voltage, high-bias mode, 25°C | VIO | 0.9 | 5 | mV | High-bias; 25°C; VO = 1.4 V, VIC = 0 V, RS = 50 Ω, RL = 10 kΩ; VDD = 5 V and 10 V | 6 | |
| Input offset voltage, high-bias mode, full range | VIO | 6.5 | mV | High-bias; full range 0°C to 70°C; VO = 1.4 V, VIC = 0 V, RS = 50 Ω, RL = 10 kΩ; VDD = 5 V and 10 V | 6 | ||
| Input offset current, high-bias mode, 25°C | IIO | 0.1 | 60 | pA | High-bias; 25°C; VO = VDD/2, VIC = VDD/2; VDD = 5 V and 10 V | 6 | |
| Input offset current, high-bias mode, 70°C | IIO | 7 | 300 | pA | High-bias; 70°C; VO = VDD/2, VIC = VDD/2; VDD = 5 V and 10 V | 6 | |
| Input bias current, high-bias mode, 25°C | IIB | 60 | pA | High-bias; 25°C; VO = VDD/2, VIC = VDD/2; VDD = 5 V and 10 V (typ 0.6 pA at 5 V, 0.7 pA at 10 V) | 6 | ||
| Input bias current, high-bias mode, 70°C | IIB | 600 | pA | High-bias; 70°C; VO = VDD/2, VIC = VDD/2; VDD = 5 V and 10 V (typ 40 pA at 5 V, 50 pA at 10 V) | 6 | ||
| Common-mode input voltage range, high-bias, full range, VDD = 5 V | VICR | -0.2 | 3.5 | V | High-bias; full range; VDD = 5 V | 6 | |
| Common-mode input voltage range, high-bias, full range, VDD = 10 V | VICR | -0.2 | 8.5 | V | High-bias; full range; VDD = 10 V | 6 | |
| High-level output voltage, high-bias, full range, VDD = 5 V | VOH | 3 | V | High-bias; full range; VID = 100 mV, RL = 10 kΩ; VDD = 5 V | 6 | ||
| High-level output voltage, high-bias, full range, VDD = 10 V | VOH | 7.8 | V | High-bias; full range; VID = 100 mV, RL = 10 kΩ; VDD = 10 V | 6 | ||
| Low-level output voltage, high-bias, 25°C | VOL | 0 | 50 | mV | High-bias; 25°C; VID = -100 mV, IOL = 0; VDD = 5 V and 10 V | 6 | |
| Large-signal differential voltage amplification, high-bias, full range, VDD = 5 V | AVD | 4 | V/mV | High-bias; full range; RL = 10 kΩ; VDD = 5 V (VO = 0.25 V to 2 V) | 6 | ||
| Large-signal differential voltage amplification, high-bias, full range, VDD = 10 V | AVD | 7.5 | V/mV | High-bias; full range; RL = 10 kΩ; VDD = 10 V (VO = 1 V to 6 V) | 6 | ||
| Common-mode rejection ratio, high-bias, 25°C | CMRR | 65 | dB | High-bias; 25°C; VIC = VICRmin; VDD = 5 V and 10 V | 6 | ||
| Supply-voltage rejection ratio, high-bias, 25°C | kSVR | 65 | dB | High-bias; 25°C; VDD = 5 V to 10 V; VO = 14 V | 6 | ||
| Supply current, high-bias, 25°C, VDD = 5 V | IDD | 675 | 1600 | µA | High-bias; 25°C; VO = VDD/2, VIC = VDD/2; no load; VDD = 5 V | 6 | |
| Supply current, high-bias, 25°C, VDD = 10 V | IDD | 950 | 2000 | µA | High-bias; 25°C; VO = VDD/2, VIC = VDD/2; no load; VDD = 10 V | 6 | |
| Input offset voltage, medium-bias mode, 25°C | VIO | 0.9 | 5 | mV | Medium-bias; 25°C; VO = 1.4 V, VIC = 0 V, RS = 50 Ω, RL = 100 kΩ; VDD = 5 V and 10 V | 22 | |
| Input offset voltage, medium-bias mode, full range | VIO | 6.5 | mV | Medium-bias; full range 0°C to 70°C; VO = 1.4 V, VIC = 0 V, RS = 50 Ω, RL = 100 kΩ; VDD = 5 V and 10 V | 22 | ||
| Input offset current, medium-bias mode, 25°C | IIO | 0.1 | 60 | pA | Medium-bias; 25°C; VO = VDD/2, VIC = VDD/2; VDD = 5 V and 10 V | 22 | |
| Input offset current, medium-bias mode, 70°C | IIO | 7 | 300 | pA | Medium-bias; 70°C; VO = VDD/2, VIC = VDD/2; VDD = 5 V and 10 V | 22 | |
| Input bias current, medium-bias mode, 25°C | IIB | 60 | pA | Medium-bias; 25°C; VO = VDD/2, VIC = VDD/2; VDD = 5 V and 10 V (typ 0.6 pA at 5 V, 0.7 pA at 10 V) | 22 | ||
| Input bias current, medium-bias mode, 70°C | IIB | 600 | pA | Medium-bias; 70°C; VO = VDD/2, VIC = VDD/2; VDD = 5 V and 10 V (typ 40 pA at 5 V, 50 pA at 10 V) | 22 | ||
| Common-mode input voltage range, medium-bias, full range, VDD = 5 V | VICR | -0.2 | 3.5 | V | Medium-bias; full range; VDD = 5 V | 22 | |
| Common-mode input voltage range, medium-bias, full range, VDD = 10 V | VICR | -0.2 | 8.5 | V | Medium-bias; full range; VDD = 10 V | 22 | |
| High-level output voltage, medium-bias, full range, VDD = 5 V | VOH | 3 | V | Medium-bias; full range; VID = 100 mV, RL = 100 kΩ; VDD = 5 V | 22 | ||
| High-level output voltage, medium-bias, full range, VDD = 10 V | VOH | 7.8 | V | Medium-bias; full range; VID = 100 mV, RL = 100 kΩ; VDD = 10 V | 22 | ||
| Low-level output voltage, medium-bias, 25°C | VOL | 0 | 50 | mV | Medium-bias; 25°C; VID = -100 mV, IOL = 0; VDD = 5 V and 10 V | 22 | |
| Large-signal differential voltage amplification, medium-bias, full range | AVD | 15 | V/mV | Medium-bias; full range; RL = 100 kΩ; VDD = 5 V and 10 V | 22 | ||
| Common-mode rejection ratio, medium-bias, 25°C | CMRR | 65 | dB | Medium-bias; 25°C; VIC = VICRmin; VDD = 5 V and 10 V | 22 | ||
| Supply-voltage rejection ratio, medium-bias, 25°C | kSVR | 70 | dB | Medium-bias; 25°C; VDD = 5 V to 10 V; VO = 14 V | 22 | ||
| Supply current, medium-bias, 25°C, VDD = 5 V | IDD | 105 | 280 | µA | Medium-bias; 25°C; VO = VDD/2, VIC = VDD/2; no load; VDD = 5 V | 22 | |
| Supply current, medium-bias, 25°C, VDD = 10 V | IDD | 143 | 300 | µA | Medium-bias; 25°C; VO = VDD/2, VIC = VDD/2; no load; VDD = 10 V | 22 | |
| Input offset voltage, low-bias mode, 25°C | VIO | 0.9 | 5 | mV | Low-bias; 25°C; VO = 1.4 V, VIC = 0 V, RS = 50 Ω, RL = 1 MΩ; VDD = 5 V and 10 V | 38 | |
| Input offset voltage, low-bias mode, full range | VIO | 6.5 | mV | Low-bias; full range 0°C to 70°C; VO = 1.4 V, VIC = 0 V, RS = 50 Ω, RL = 1 MΩ; VDD = 5 V and 10 V | 38 | ||
| Input offset current, low-bias mode, 25°C | IIO | 0.1 | 60 | pA | Low-bias; 25°C; VO = VDD/2, VIC = VDD/2; VDD = 5 V and 10 V | 38 | |
| Input offset current, low-bias mode, 70°C | IIO | 300 | pA | Low-bias; 70°C; VO = VDD/2, VIC = VDD/2; VDD = 5 V and 10 V (typ 7 pA at 5 V, 8 pA at 10 V) | 38 | ||
| Input bias current, low-bias mode, 25°C | IIB | 60 | pA | Low-bias; 25°C; VO = VDD/2, VIC = VDD/2; VDD = 5 V and 10 V (typ 0.6 pA at 5 V, 0.7 pA at 10 V) | 38 | ||
| Input bias current, low-bias mode, 70°C | IIB | 600 | pA | Low-bias; 70°C; VO = VDD/2, VIC = VDD/2; VDD = 5 V and 10 V (typ 40 pA at 5 V, 50 pA at 10 V) | 38 | ||
| Common-mode input voltage range, low-bias, full range, VDD = 5 V | VICR | -0.2 | 3.5 | V | Low-bias; full range; VDD = 5 V | 38 | |
| Common-mode input voltage range, low-bias, full range, VDD = 10 V | VICR | -0.2 | 8.5 | V | Low-bias; full range; VDD = 10 V | 38 | |
| High-level output voltage, low-bias, full range, VDD = 5 V | VOH | 3 | V | Low-bias; full range; VID = 100 mV, RL = 1 MΩ; VDD = 5 V | 38 | ||
| High-level output voltage, low-bias, full range, VDD = 10 V | VOH | 7.8 | V | Low-bias; full range; VID = 100 mV, RL = 1 MΩ; VDD = 10 V | 38 | ||
| Low-level output voltage, low-bias, 25°C | VOL | 0 | 50 | mV | Low-bias; 25°C; VID = -100 mV, IOL = 0; VDD = 5 V and 10 V | 38 | |
| Large-signal differential voltage amplification, low-bias, full range | AVD | 50 | V/mV | Low-bias; full range; RL = 1 MΩ; VDD = 5 V and 10 V | 38 | ||
| Common-mode rejection ratio, low-bias, 25°C | CMRR | 65 | dB | Low-bias; 25°C; VIC = VICRmin; VDD = 5 V and 10 V | 38 | ||
| Supply-voltage rejection ratio, low-bias, 25°C | kSVR | 70 | dB | Low-bias; 25°C; VDD = 5 V to 10 V; VO = 14 V | 38 | ||
| Supply current, low-bias, 25°C, VDD = 5 V | IDD | 10 | 17 | µA | Low-bias; 25°C; VO = VDD/2, VIC = VDD/2; no load; VDD = 5 V | 38 | |
| Supply current, low-bias, 25°C, VDD = 10 V | IDD | 14 | 23 | µA | Low-bias; 25°C; VO = VDD/2, VIC = VDD/2; no load; VDD = 10 V | 38 | |
| Supply voltage | VDD | 18 | V | All voltage values referenced to network ground (Note 1) | 5 | ||
| Input voltage range (any input) | VI | -0.3 | V | Any input; upper limit printed as VDD | 5 | ||
| Input current | II | -5 | 5 | mA | ±5 mA | 5 | |
| Output current | IO | -30 | 30 | mA | ±30 mA | 5 | |
| Supply voltage (C suffix) | VDD | 3 | 16 | V | C suffix (TLC271AC) | 5 | |
| Common-mode input voltage, VDD = 5 V (C suffix) | VIC | -0.2 | 3.5 | V | C suffix; VDD = 5 V | 5 | |
| Common-mode input voltage, VDD = 10 V (C suffix) | VIC | -0.2 | 8.5 | V | C suffix; VDD = 10 V | 5 | |
| Operating free-air temperature (C suffix) | TA | 0 | 70 | °C | C suffix | 5 | |
| Power rating, P package | 1000 | mW | P package; TA ≤ 25°C | 5 | |||
| Derating factor above TA = 25°C, P package | 8 | mW/°C | P package; derating above TA = 25°C | 5 |
CAD (KiCad official)
- Symbol:
TLC271ACP - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files:
tlc271acp-etched.step/tlc271acp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlc271acp.step/tlc271acp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (86 pp, sha256
462161034a481a4b, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).