component
AD5644RBRMZ-3
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownAD5644RBRMZ-3
Analog Devices · Digital To Analog Converters (DACs) · MSOP-10
AD5644RBRMZ-3 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. |
| 2 | VOUTB | output | Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. |
| 3 | GND | power_in | Ground Reference Point for all Circuitry on the Part. |
| 4 | VOUTC | output | Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. |
| 5 | VOUTD | output | Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. |
| 6 | SYNC | input | Active Low Control Input that is the frame synchronization signal for the input data; data is transferred in on the falling edges of the next 24 clocks, and if SYNC is taken high before the 24th falling edge the write sequence is ignored. |
| 7 | SCLK | input | Serial Clock Input; data is clocked into the input shift register on the falling edge of the serial clock, and data can be transferred at rates up to 50 MHz. |
| 8 | DIN | input | Serial Data Input for a 24-bit shift register; data is clocked into the register on the falling edge of the serial clock input. |
| 9 | VDD | power_in | Power Supply Input that can be operated from 2.7 V to 5.5 V and should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. |
| 10 | VREFIN/VREFOUT | bidirectional | Common pin for reference input and reference output; it is the reference output when the internal reference is used and the reference input when an external reference is used, defaulting to reference input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10 |
| Category | ADC/DAC/Data Conversion |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD to GND | VDD | -0.3 | 7 | V | 8 | ||
| VOUT to GND | VOUT | -0.3 | V | Upper limit printed as VDD + 0.3 V | 8 | ||
| VREFIN/VREFOUT to GND | VREFIN/VREFOUT | -0.3 | V | Upper limit printed as VDD + 0.3 V | 8 | ||
| Digital Input Voltage to GND | -0.3 | V | Upper limit printed as VDD + 0.3 V | 8 | |||
| Operating Temperature Range (Industrial) | -40 | 105 | °C | 8 | |||
| Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Junction Temperature (TJ max) | TJ | 150 | °C | 8 | |||
| Thermal Impedance, junction-to-ambient (MSOP, 4-layer board) | θJA | 142 | °C/W | MSOP Package (4-Layer Board) | 8 | ||
| Thermal Impedance, junction-to-case (MSOP) | θJC | 43.7 | °C/W | MSOP Package | 8 | ||
| Relative Accuracy (INL), AD5644R | INL | -4 | 2 | 4 | LSB | 4 | |
| Differential Nonlinearity, AD5644R | DNL | 0.5 | LSB | Guaranteed monotonic by design | 4 | ||
| Zero-Code Error | 2 | 10 | mV | All zeroes loaded to DAC register | 4 | ||
| Offset Error | -10 | 1 | 10 | mV | 4 | ||
| Full-Scale Error | -0.1 | 1 | % of FSR | All ones loaded to DAC register | 4 | ||
| Gain Error | 1.5 | % of FSR | 4 | ||||
| Zero-Code Error Drift | 2 | μV/°C | 4 | ||||
| Gain Temperature Coefficient | 2.5 | ppm of FSR/°C | 4 | ||||
| DC Power Supply Rejection Ratio | PSRR | -100 | dB | DAC code = midscale; VDD = 3 V ± 10% | 4 | ||
| DC Crosstalk, External Reference, full-scale output change | 10 | μV | Due to full-scale output change, RL = 2 kΩ to GND or VDD | 4 | |||
| DC Crosstalk, External Reference, load current change | 10 | μV/mA | Due to load current change | 4 | |||
| DC Crosstalk, External Reference, powering down | 5 | μV | Due to powering down (per channel) | 4 | |||
| DC Crosstalk, Internal Reference, full-scale output change | 25 | μV | Due to full-scale output change, RL = 2 kΩ to GND or VDD | 4 | |||
| DC Crosstalk, Internal Reference, load current change | 20 | μV/mA | Due to load current change | 4 | |||
| DC Crosstalk, Internal Reference, powering down | 10 | μV | Due to powering down (per channel) | 4 | |||
| Output Voltage Range | VOUT | 0 | V | Upper limit printed as VDD | 5 | ||
| Capacitive Load Stability | CL | 2 | nF | RL = ∞ | 5 | ||
| Capacitive Load Stability | CL | 10 | nF | RL = 2 kΩ | 5 | ||
| DC Output Impedance | 0.5 | Ω | 5 | ||||
| Short-Circuit Current | 30 | mA | VDD = 3 V | 5 | |||
| Power-Up Time | 4 | μs | Coming out of power-down mode; VDD = 3 V | 5 | |||
| Reference Current | 170 | 200 | μA | VREF = VDD = 3.6 V | 5 | ||
| Reference Input Range | 0 | V | Upper limit printed as VDD | 5 | |||
| Reference Input Impedance | 26 | kΩ | 5 | ||||
| Reference Output Voltage | 1.247 | 1.253 | V | At ambient | 5 | ||
| Reference Temperature Coefficient, MSOP package models | TC | -5 | 5 | 15 | ppm/°C | MSOP package models | 5 |
| Reference Output Impedance | 7.5 | kΩ | 5 | ||||
| Input Current | -2 | 2 | μA | All digital inputs | 5 | ||
| VINL, Input Low Voltage | VINL | 0.8 | V | VDD = 3 V | 5 | ||
| VINH, Input High Voltage | VINH | 2 | V | VDD = 3 V | 5 | ||
| Pin Capacitance | 3 | pF | 5 | ||||
| VDD Supply Voltage | VDD | 2.7 | 3.6 | V | 5 | ||
| IDD Normal Mode, internal reference off | IDD | 0.44 | 0.85 | mA | VIH = VDD, VIL = GND, VDD = 2.7 V to 3.6 V; internal reference off | 5 | |
| IDD Normal Mode, internal reference on | IDD | 0.95 | 1.15 | mA | VIH = VDD, VIL = GND, VDD = 2.7 V to 3.6 V; internal reference on | 5 | |
| IDD All Power-Down Modes | IDD | 0.2 | 1 | μA | VIH = VDD, VIL = GND, VDD = 2.7 V to 3.6 V | 5 | |
| Output Voltage Settling Time, AD5644R | 3.5 | 5 | μs | ¼ to ¾ scale settling to ±0.5 LSB | 6 | ||
| Output Voltage Settling Time, AD5624R | 3 | 4.5 | μs | ¼ to ¾ scale settling to ±0.5 LSB | 6 | ||
| Output Voltage Settling Time, AD5664R | 4 | 7 | μs | ¼ to ¾ scale settling to ±2 LSB | 6 | ||
| Slew Rate | 1.8 | V/μs | 6 | ||||
| Digital-to-Analog Glitch Impulse | 10 | nV-s | 1 LSB change around major carry | 6 | |||
| Multiplying Bandwidth | 340 | kHz | VREF = 2 V ± 0.1 V p-p | 6 | |||
| Total Harmonic Distortion | THD | -80 | dB | VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz | 6 | ||
| SCLK Cycle Time | t1 | 20 | ns | VDD = 2.7 V to 5.5 V | 7 | ||
| SCLK High Time | t2 | 9 | ns | VDD = 2.7 V to 5.5 V | 7 | ||
| SCLK Low Time | t3 | 9 | ns | VDD = 2.7 V to 5.5 V | 7 | ||
| SYNC to SCLK Falling Edge Setup Time | t4 | 13 | ns | VDD = 2.7 V to 5.5 V | 7 | ||
| Data Setup Time | t5 | 5 | ns | VDD = 2.7 V to 5.5 V | 7 |
CAD (KiCad official)
- Symbol:
AD5644RBRMZ-3 - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
ad5644rbrmz-3-etched.step/ad5644rbrmz-3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5644rbrmz-3.step/ad5644rbrmz-3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
a50d3043badbd5d0, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).