component
STN4900
Public Made by Adomby adom
STANSON Tech MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTN4900
STANSON Tech · MOSFETs · SOP-8
STN4900 from STANSON Tech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of N-channel MOSFET 1. |
| 2 | G1 | input | Gate of N-channel MOSFET 1, with VGS rated ±20V. |
| 3 | S2 | passive | Source of N-channel MOSFET 2. |
| 4 | G2 | input | Gate of N-channel MOSFET 2, with VGS rated ±20V. |
| 5 | D2 | passive | Drain of N-channel MOSFET 2, with VDSS rated 60V; tied with pin 6. |
| 6 | D2 | passive | Drain of N-channel MOSFET 2, with VDSS rated 60V; tied with pin 5. |
| 7 | D1 | passive | Drain of N-channel MOSFET 1, with VDSS rated 60V; tied with pin 8. |
| 8 | D1 | passive | Drain of N-channel MOSFET 1, with VDSS rated 60V; tied with pin 7. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STANSON Tech |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gate-Source Voltage | VGSS | -20 | 20 | V | 2 | ||
| Operation Junction Temperature | TJ | -55 | 150 | ℃ | 2 | ||
| Storage Temperature Range | TSTG | -55 | 150 | ℃ | 2 | ||
| Drain-Source Breakdown Voltage | V(BR)DSS | 60 | V | VGS=0V,ID=250uA | 3 | ||
| Gate Threshold Voltage | VGS(th) | 0.5 | 1.5 | V | VDS=VGS,ID=250 uA | 3 | |
| Gate Leakage Current | IGSS | -100 | 100 | nA | VDS=0V,VGS=±20V | 3 | |
| Zero Gate Voltage Drain Current (TJ=55℃) | IDSS | 1 | uA | TJ=55℃, VDS=20V,VGS=0V | 3 | ||
| Zero Gate Voltage Drain Current | IDSS | 5 | uA | VDS=20V,VGS=0V | 3 | ||
| Drain-source On-Resistance | RDS(on) | 0.11 | 0.118 | Ω | VGS=10V, ID=5.3A | 3 | |
| Drain-source On-Resistance | RDS(on) | 0.115 | 0.125 | Ω | VGS=4.5V, ID=4.3A | 3 | |
| Forward Tran Conductance | gfs | 15 | S | VDS=15V,ID=4.3A | 3 | ||
| Diode Forward Voltage | VSD | 0.8 | 1.2 | V | IS=1.7A,VGS=0V | 3 | |
| Total Gate Charge | Qg | 15 | 20 | nC | VDS=30V,VGS=5V, ID≡4.3A | 3 | |
| Turn-On Delay Time | td(on) | 10 | 20 | nS | VDD=30V,RL=8.8Ω, ID=3.4A,VGEN=10V, RG=1Ω | 3 | |
| Turn-On Rise Time | tr | 15 | 25 | nS | VDD=30V,RL=8.8Ω, ID=3.4A,VGEN=10V, RG=1Ω | 3 | |
| Turn-Off Delay Time | td(off) | 25 | 35 | nS | VDD=30V,RL=8.8Ω, ID=3.4A,VGEN=10V, RG=1Ω | 3 | |
| Turn-Off Fall Time | tf | 12 | 20 | nS | VDD=30V,RL=8.8Ω, ID=3.4A,VGEN=10V, RG=1Ω | 3 | |
| Drain-Source Voltage | VDSS | 60 | V | 2 | |||
| Continuous Drain Current | ID | 4.2 | A | TJ=150℃; TA=25℃ | 2 | ||
| Continuous Drain Current | ID | 3.2 | A | TJ=150℃; TA=70℃ | 2 | ||
| Pulsed Drain Current | IDM | 20 | A | 2 | |||
| Continuous Source Current (Diode Conduction) | IS | 11 | A | 2 | |||
| Power Dissipation | PD | 2.5 | W | TA=25℃ | 2 | ||
| Power Dissipation | PD | 1.6 | W | TA=70℃ | 2 | ||
| Thermal Resistance-Junction to Ambient | RθJA | 80 | ℃/W | 2 |
CAD (KiCad official)
- Symbol:
STN4900 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
stn4900-etched.step/stn4900-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stn4900.step/stn4900.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STANSON Tech datasheet (8 pp, sha256
195b8b6167635197, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).