component
TLV62568DBVR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTLV62568DBVR
Texas Instruments · DC-DC Converters · SOT-23-5
TLV62568DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Device enable logic input. Logic high (VIH ≥ 0.95 V typ, 1.2 V max) enables the converter; logic low (VIL ≤ 0.85 V typ) forces the device into shutdown. Do not leave floating. |
| 2 | GND | power_in | Device ground reference; all voltage measurements are with respect to this pin. Connect to the system ground plane. |
| 3 | SW | power_out | Switch node connected to the internal high-side and low-side FETs and to the external inductor terminal. Absolute-max: -0.3 V to VIN+0.3 V DC, -3.0 V to 9 V AC (<10 ns). Connect the inductor of the output LC filter here. |
| 4 | VIN | power_in | Power supply voltage input, 2.5 V to 5.5 V recommended (absolute-max 6 V). Bypass with a low-ESR ceramic capacitor (typ 4.7 µF) close to the pin. |
| 5 | FB | input | Feedback input for the internal control loop; regulates to VFB = 0.6 V (typ, 0.588-0.612 V). Connect to the midpoint of an external resistor divider from VOUT to GND to set the output voltage. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | PMIC |
| Pins | 5 |
Ordering variants
Same part, different packaging or reel option.
TLV62568DBVRTLV62568DBVRDBVTTLV62568DBVRDDCRTLV62568DBVRDDCTTLV62568DBVRDRLR
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage on VIN, EN, PG pins | VIN, EN, PG | -0.3 | 6 | V | 4 | ||
| Voltage on FB pin | FB | -0.3 | 5.5 | V | 4 | ||
| SW voltage (DC) | SW (DC) | -0.3 | V | 4 | |||
| SW voltage (AC) | SW (AC) | -3 | 9 | V | less than 10 ns | 4 | |
| Operating junction temperature (absolute maximum range) | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Human-body model ESD rating | V(ESD) HBM | -2000 | 2000 | V | ANSI/ESDA/JEDEC JS-001 | 4 | |
| Charged-device model ESD rating | V(ESD) CDM | -500 | 500 | V | JEDEC JESD22-C101 | 4 | |
| Input voltage | VIN | 2.5 | 5.5 | V | 4 | ||
| Output voltage | VOUT | 0.6 | V | 4 | |||
| Output current | IOUT | 1 | A | 4 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Quiescent current into VIN pin | IQ | 35 | uA | Not switching | 5 | ||
| Shutdown current into VIN pin | ISD | 0.1 | 2 | µA | EN = 0 V | 5 | |
| Under voltage lock out, VIN falling | VUVLO | 2.3 | 2.45 | V | VIN falling | 5 | |
| Under voltage lock out hysteresis | 100 | mV | 5 | ||||
| Thermal shutdown threshold, rising | TJSD | 150 | °C | Junction temperature rising | 5 | ||
| Thermal shutdown threshold, falling | TJSD | 130 | °C | Junction temperature falling | 5 | ||
| High-level threshold at EN pin | VIH | 0.95 | 1.2 | V | 2.5 V ≤ VIN ≤ 5.5 V | 5 | |
| Low-level threshold at EN pin | VIL | 0.4 | 0.85 | V | 2.5 V ≤ VIN ≤ 5.5 V | 5 | |
| Soft startup time | tSS | 700 | µs | TLV62568DBV column | 5 | ||
| Feedback regulation voltage | VFB | 0.588 | 0.6 | 0.612 | V | 5 | |
| High-side FET on resistance | RDS(on) | 150 | mΩ | High-side FET | 5 | ||
| Low-side FET on resistance | RDS(on) | 100 | mΩ | Low-side FET | 5 | ||
| High-side FET current limit | ILIM | 1.5 | A | 5 | |||
| Switching frequency | fSW | 1.5 | MHz | VOUT = 1.8 V | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 191.6 | °C/W | DBV (5 pins) package | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 141.4 | °C/W | DBV (5 pins) package | 4 | ||
| Junction-to-board thermal resistance | RθJB | 44.5 | °C/W | DBV (5 pins) package | 4 | ||
| Junction-to-top characterization parameter | ψJT | 34.5 | °C/W | DBV (5 pins) package | 4 | ||
| Junction-to-board characterization parameter | ψJB | 43.9 | °C/W | DBV (5 pins) package | 4 |
CAD (KiCad official)
- Symbol:
TLV62568DBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tlv62568dbvr-etched.step/tlv62568dbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv62568dbvr.step/tlv62568dbvr.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
tlv62568dbvr.step |
85 KB | You want the bare part, or you mark your own boards. |
tlv62568dbvr-etched.step |
2.3 MB | You want the part with TLV62568DBVR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 546 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
091461b54cc26fbe, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).