AD5667BRMZ from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VOUTA	output	Analog output voltage from DAC A; the output amplifier has rail-to-rail operation, giving an output range of 0 V to VDD.
2	VOUTB	output	Analog output voltage from DAC B; the output amplifier has rail-to-rail operation, giving an output range of 0 V to VDD.
3	GND	power_in	Ground reference point for all circuitry on the device.
4	LDAC	input	Pulsing this pin low allows any or all DAC registers to be updated if the inputs have new data, or this pin can be tied permanently low.
5	CLR	input	Asynchronous, falling-edge sensitive clear input; while CLR is low all LDAC pulses are ignored, and activating it loads zero scale to all input and DAC registers, clearing the output to 0 V.
6	ADDR	input	Three-state address input that sets the two least significant bits (A1, A0) of the 7-bit slave address.
7	SCL	input	Serial clock line used in conjunction with SDA to clock data into or out of the 24-bit input register.
8	SDA	bidirectional	Bidirectional, open-drain serial data line that should be pulled to the supply with an external pull-up resistor.
9	VDD	power_in	Power supply input operated from 2.7 V to 5.5 V, to be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
10	VREFIN	input	Reference input pin only on the AD5627/AD5667 (no VREFOUT function), where the external reference applied here sets the DAC output range.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	MSOP-10
Category	ADC/DAC/Data Conversion
Pins	10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Relative Accuracy		-12	8	12	LSB	AD5667R/AD5667 (16-bit) linearity, reduced code range 512 to 65,024	3
Differential Nonlinearity		-1		1	LSB	Guaranteed monotonic by design	3
Offset Error		-10	1	10	mV		3
Zero-Code Error			2	10	mV	All 0s loaded to DAC register	3
Full-Scale Error		-1	-0.1	1	% of FSR	All 1s loaded to DAC register	3
Gain Error		-1.5		1.5	% of FSR		3
Zero-Code Error Drift		-2		2	µV/°C		3
Gain Temperature Coefficient		-2.5		2.5	ppm Of FSR/°C		3
Capacitive Load Stability				2	nF	RL = ∞	3
Capacitive Load Stability				10	nF	RL = 2 kΩ	3
Short-Circuit Current			30		mA	VDD = 5 V	3
Reference Current			110	130	µA	VREF = VDD = 5.5 V	3
Input Current (ADDR, CLR, LDAC)	IIN	-1		1	µA		4
Input Low Voltage (ADDR, CLR, LDAC)	VINL			0.15	× VDD		4
Input High Voltage (ADDR, CLR, LDAC)	VINH	0.85			× VDD		4
Input Current (SDA, SCL)	IIN	-1		1	µA		4
Input Low Voltage (SDA, SCL)	VINL			0.3	× VDD		4
Input High Voltage (SDA, SCL)	VINH	0.7			× VDD		4
Output Low Voltage	VOL			0.4	V	ISINK = 3 mA	4
Output Low Voltage	VOL			0.6	V	ISINK = 6 mA	4
Floating-State Leakage Current		-1		1	µA		4
Supply Voltage	VDD	2.7		5.5	V		4
Normal Mode Supply Current	IDD		0.4	0.5	mA	VDD = 4.5 V to 5.5 V, internal reference off	4
Normal Mode Supply Current	IDD		0.35	0.45	mA	VDD = 2.7 V to 3.6 V, internal reference off	4
Power-Down Mode Supply Current	IDD		0.48	1	µA	All Power-Down Modes, VIH = VDD, VIL = GND	4
Output Voltage Settling Time			4	7	µs	AD5667R/AD5667, ¼ to ¾ scale settling to ±2 LSB	5
Slew Rate			1.8		V/µs		5
Digital-to-Analog Glitch Impulse			15		nV-s	1 LSB change around major carry transition	5
Multiplying Bandwidth			340		kHz	VREF = 2 V ± 0.1 V p-p	5
Total Harmonic Distortion			-80		dB	VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz	5
Output Noise Spectral Density			120		nV/√Hz	DAC code = midscale, 1 kHz	5
Digital Supply Voltage Absolute Maximum (VDD to GND)	VDD	-0.3		7	V	VDD to GND	8
Operating Temperature Range, Industrial		-40		105	°C		8
Storage Temperature Range		-65		150	°C		8
Junction Temperature (TJ maximum)	TJ			150	°C		8
Thermal Impedance θJA	θJA		150.4		°C/W	MSOP Package	8

CAD (KiCad official)

Symbol: AD5667BRMZ
Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
3D model: MSOP-10 (KiCad packages3D, STEP)
3D model files: ad5667brmz-etched.step / ad5667brmz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5667brmz.step / ad5667brmz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (30 pp, sha256 dd375772240388df, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5667BRMZ

Verified AD5667BRMZ

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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