component
74LV541ATPWJ
Public Made by Adomby adom
Nexperia Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74LV541ATPWJ
Nexperia · Buffers, Drivers, Receivers, Transceivers · TSSOP-20
74LV541ATPWJ from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Output enable input, active LOW; a HIGH causes the associated outputs to assume a high-impedance OFF-state. |
| 2 | A0 | input | Data input, TTL compatible with Schmitt-trigger action; VIH minimum 2 V and VIL maximum 0.8 V at VCC = 4.5 V to 5.5 V. |
| 3 | A1 | input | Data input, TTL compatible with Schmitt-trigger action; VIH minimum 2 V and VIL maximum 0.8 V at VCC = 4.5 V to 5.5 V. |
| 4 | A2 | input | Data input, TTL compatible with Schmitt-trigger action; VIH minimum 2 V and VIL maximum 0.8 V at VCC = 4.5 V to 5.5 V. |
| 5 | A3 | input | Data input, TTL compatible with Schmitt-trigger action; VIH minimum 2 V and VIL maximum 0.8 V at VCC = 4.5 V to 5.5 V. |
| 6 | A4 | input | Data input, TTL compatible with Schmitt-trigger action; VIH minimum 2 V and VIL maximum 0.8 V at VCC = 4.5 V to 5.5 V. |
| 7 | A5 | input | Data input, TTL compatible with Schmitt-trigger action; VIH minimum 2 V and VIL maximum 0.8 V at VCC = 4.5 V to 5.5 V. |
| 8 | A6 | input | Data input, TTL compatible with Schmitt-trigger action; VIH minimum 2 V and VIL maximum 0.8 V at VCC = 4.5 V to 5.5 V. |
| 9 | A7 | input | Data input, TTL compatible with Schmitt-trigger action; VIH minimum 2 V and VIL maximum 0.8 V at VCC = 4.5 V to 5.5 V. |
| 10 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 11 | Y7 | output | Data output, 3-state; high-impedance OFF-state when OE1 is HIGH or OE2 is HIGH. |
| 12 | Y6 | output | Data output, 3-state; high-impedance OFF-state when OE1 is HIGH or OE2 is HIGH. |
| 13 | Y5 | output | Data output, 3-state; high-impedance OFF-state when OE1 is HIGH or OE2 is HIGH. |
| 14 | Y4 | output | Data output, 3-state; high-impedance OFF-state when OE1 is HIGH or OE2 is HIGH. |
| 15 | Y3 | output | Data output, 3-state; high-impedance OFF-state when OE1 is HIGH or OE2 is HIGH. |
| 16 | Y2 | output | Data output, 3-state; high-impedance OFF-state when OE1 is HIGH or OE2 is HIGH. |
| 17 | Y1 | output | Data output, 3-state; high-impedance OFF-state when OE1 is HIGH or OE2 is HIGH. |
| 18 | Y0 | output | Data output, 3-state; high-impedance OFF-state when OE1 is HIGH or OE2 is HIGH. |
| 19 | OE2 | input | Output enable input, active LOW; a HIGH causes the associated outputs to assume a high-impedance OFF-state. |
| 20 | VCC | power_in | Supply voltage; recommended operating range 4.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | 4.5 | 5.5 | V | 4 | ||
| input voltage | VI | 0 | 5.5 | V | 4 | ||
| output voltage active mode | VO | 0 | V | active mode; max printed as VCC | 4 | ||
| output voltage power-down or 3-state mode | VO | 0 | 5.5 | V | power-down or 3-state mode | 4 | |
| ambient temperature | Tamb | -40 | 125 | °C | 4 | ||
| input transition rise and fall rate | Δt/ΔV | 20 | ns/V | VCC = 5.0 V ± 0.5 V | 4 | ||
| supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| input voltage | VI | -0.5 | 7 | V | 4 | ||
| output voltage active mode | VO | -0.5 | V | active mode; max printed as VCC + 0.5 V | 4 | ||
| output voltage power-down or 3-state mode | VO | -0.5 | 7 | V | power-down or 3-state mode | 4 | |
| input clamping current | IIK | -20 | mA | VI < 0 V | 4 | ||
| output clamping current | IOK | -50 | mA | VO < 0 V | 4 | ||
| output current | IO | -35 | 35 | mA | VO = 0 V to VCC | 4 | |
| supply current | ICC | 70 | mA | 4 | |||
| ground current | IGND | -70 | mA | 4 | |||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 4 | ||
| HIGH-level input voltage | VIH | 2 | V | VCC = 4.5 V to 5.5 V | 5 | ||
| LOW-level input voltage | VIL | 0.8 | V | VCC = 4.5 V to 5.5 V | 5 | ||
| HIGH-level output voltage | VOH | 4.4 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -50 μA | 5 | ||
| HIGH-level output voltage | VOH | 3.8 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -16 mA | 5 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 50 μA | 5 | |
| LOW-level output voltage | VOL | 0.55 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 16 mA | 5 | ||
| OFF-state output current | IOZ | -2.5 | 2.5 | μA | VCC = 5.5 V; VI = VIH or VIL; VO = GND to 5.5 V | 5 | |
| power-off leakage current | IOFF | 5 | μA | VI or VO = GND to 5.5 V; VCC = 0 V | 5 | ||
| input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 0 V to 5.5 V | 5 | |
| supply current | ICC | 20 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V | 5 | ||
| additional supply current | ΔICC | 1.5 | mA | per input pin; VI = 3.4 V; IO = 0 A; other pins at VCC or GND; VCC = 5.5 V | 5 | ||
| propagation delay An to Yn | tpd | 1 | 2.8 | 9 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF | 6 |
| propagation delay An to Yn | tpd | 1 | 4 | 10 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF | 6 |
| enable time OEn to Yn | ten | 1 | 3.9 | 14 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF | 6 |
| enable time OEn to Yn | ten | 1 | 5.2 | 15.2 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF | 6 |
| disable time OEn to Yn | tdis | 1 | 3.6 | 8.5 | ns | VCC = 4.5 V to 5.5 V; CL = 15 pF | 6 |
| disable time OEn to Yn | tdis | 1 | 5.7 | 14 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF | 6 |
| skew | tsk(o) | 1 | ns | VCC = 4.5 V to 5.5 V; CL = 50 pF | 6 | ||
| input capacitance | CI | 2 | 6 | pF | VI = VCC or GND; VCC = 5 V | 6 | |
| LOW-level output voltage (peak) | VOL(p) | 0.6 | 1.5 | V | VCC = 5 V; CL = 50 pF; Tamb = 25 °C | 6 | |
| LOW-level output voltage (valley) | VOL(v) | -1.5 | -0.6 | V | VCC = 5 V; CL = 50 pF; Tamb = 25 °C | 6 | |
| AC HIGH-level input voltage (dynamic) | VIH(AC) | 2 | V | VCC = 5 V; CL = 50 pF; Tamb = 25 °C | 6 | ||
| AC LOW-level input voltage (dynamic) | VIL(AC) | 0.8 | V | VCC = 5 V; CL = 50 pF; Tamb = 25 °C | 6 |
CAD (KiCad official)
- Symbol:
74LV541ATPWJ - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
74lv541atpwj-etched.step/74lv541atpwj-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lv541atpwj.step/74lv541atpwj.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
bde7add89f8d289c, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).