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TPS54316PWP
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Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS54316PWP
Texas Instruments · DC-DC Converters · HTSSOP-20-EP
TPS54316PWP from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog ground and return for the compensation network, output divider, slow-start capacitor, VBIAS capacitor, RT resistor and FSEL pin; make the PowerPAD connection to AGND. |
| 2 | VSENSE | input | Error amplifier inverting input, to be connected directly to the output voltage sense point. |
| 3 | NC | unconnected | No internal connection. |
| 4 | PWRGD | output | Open-drain powergood output that is high-impedance when VSENSE is at or above 90% of Vref and otherwise low, and is low when SS/ENA is low or an internal shutdown is active. |
| 5 | BOOT | input | Bootstrap input; a 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates the floating drive for the high-side FET driver. |
| 6 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor. |
| 7 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor. |
| 8 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor. |
| 9 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor. |
| 10 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor. |
| 11 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns. |
| 12 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns. |
| 13 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns. |
| 14 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and bypassed to PGND with a 1-µF to 10-µF low-ESR ceramic capacitor. |
| 15 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and bypassed to PGND with a 1-µF to 10-µF low-ESR ceramic capacitor. |
| 16 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and bypassed to PGND with a 1-µF to 10-µF low-ESR ceramic capacitor. |
| 17 | VBIAS | power_out | Internal bias regulator output supplying the internal circuitry, to be bypassed to AGND with a 0.1-µF to 1.0-µF low-ESR ceramic capacitor. |
| 18 | SS/ENA | bidirectional | Dual-function slow-start/enable pin: a logic input that enables or disables operation and a capacitor input that sets the start-up time. |
| 19 | FSEL | input | Logic input that selects between the two internally set switching frequencies. |
| 20 | RT | input | Frequency-setting resistor input; connect a resistor from RT to AGND to set the switching frequency fs. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN, SS/ENA, SYNC input voltage (absolute maximum) | VI | -0.3 | 7 | V | 4 | ||
| RT input voltage (absolute maximum) | VI | -0.3 | 6 | V | 4 | ||
| VSENSE input voltage (absolute maximum) | VI | -0.3 | 4 | V | 4 | ||
| BOOT input voltage (absolute maximum) | VI | -0.3 | 17 | V | 4 | ||
| VBIAS, PWRGD, COMP output voltage (absolute maximum) | VO | -0.3 | 7 | V | 4 | ||
| PH output voltage (absolute maximum) | VO | -0.6 | 10 | V | 4 | ||
| COMP, VBIAS source current (absolute maximum) | IO | 6 | mA | 4 | |||
| PH sink current (absolute maximum) | IS | 6 | A | 4 | |||
| COMP sink current (absolute maximum) | IS | 6 | mA | 4 | |||
| SS/ENA, PWRGD sink current (absolute maximum) | IS | 10 | mA | 4 | |||
| Voltage differential AGND to PGND (absolute maximum) | -0.3 | 0.3 | V | 4 | |||
| Operating virtual junction temperature (absolute maximum) | TJ | -40 | 125 | °C | 4 | ||
| Storage temperature (absolute maximum) | Tstg | -65 | 150 | °C | 4 | ||
| Input voltage range (recommended operating) | VI | 3 | 6 | V | 4 | ||
| Operating junction temperature (recommended operating) | TJ | -40 | 125 | °C | 4 | ||
| Input voltage range | VIN | 3 | 6 | V | 5 | ||
| Quiescent current, fs = 350 kHz | I(Q) | 6.2 | 9.6 | mA | fs = 350 kHz, FSEL ≤ 0.8 V, RT open | 5 | |
| Quiescent current, shutdown | I(Q) | 1 | 1.4 | mA | Shutdown, SS/ENA = 0 V | 5 | |
| Quiescent current, fs = 550 kHz | I(Q) | 8.4 | 12.8 | mA | fs = 550 kHz, FSEL ≤ 2.5 V, RT open, Phase pin open | 5 | |
| UVLO start threshold voltage | 2.95 | 3 | V | 5 | |||
| UVLO stop threshold voltage | 2.7 | 2.8 | V | 5 | |||
| UVLO hysteresis voltage | 0.14 | 0.16 | V | 5 | |||
| VBIAS output voltage | VBIAS | 2.7 | 2.8 | 2.9 | V | I(VBIAS) = 0 | 5 |
| VBIAS output current | 100 | µA | Static resistive loads only | 5 | |||
| Output voltage TPS54316 (3.3 V) | VO | 3.3 | V | TJ = 25°C, VIN = 5 V | 5 | ||
| Output voltage tolerance TPS54316 | VO | -2.5 | 2.5 | % | 4 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −40° ≤ TJ ≤ 125°C | 5 | |
| Line regulation | 0.21 | %/V | IL = 3 A, 350 ≤ fs ≤ 550 kHz, TJ = 85°C | 5 | |||
| Load regulation | 0.21 | %/A | IL = 0 A to 3 A, 350 ≤ fs ≤ 550 kHz, TJ = 85°C | 5 | |||
| Internally set free-running frequency, FSEL low | 280 | 350 | 420 | kHz | FSEL ≤ 0.8 V, RT open | 5 | |
| Internally set free-running frequency, FSEL high | 440 | 550 | 660 | kHz | FSEL ≥ 2.5 V, RT open | 5 | |
| Externally set free-running frequency | 252 | 280 | 308 | kHz | RT = 180 kΩ (1% resistor to AGND) | 5 | |
| Externally set free-running frequency | 460 | 500 | 540 | kHz | RT = 100 kΩ (1% resistor to AGND) | 5 | |
| Externally set free-running frequency | 663 | 700 | 762 | kHz | RT = 68 kΩ (1% resistor to AGND) | 5 | |
| Minimum controllable on time | 200 | ns | 5 | ||||
| Maximum duty cycle | 90 | % | 5 | ||||
| Error amplifier unity gain bandwidth | 3 | 5 | MHz | 6 | |||
| PWM comparator propagation delay (PWM comparator input to PH pin, excluding dead time) | 70 | 85 | ns | 10-mV overdrive | 6 | ||
| Enable threshold voltage, SS/ENA | 0.82 | 1.2 | 1.4 | V | 6 | ||
| Internal slow-start time TPS54316 | 4.7 | 6.1 | 7.6 | ms | 6 | ||
| Charge current, SS/ENA | 3 | 5 | 8 | µA | SS/ENA = 0 V | 6 | |
| Discharge current, SS/ENA | 1.5 | 2.3 | 4 | mA | SS/ENA = 0.2 V, VI = 1.5 V | 6 | |
| Output saturation voltage, PWRGD | 0.18 | 0.3 | V | I(sink) = 2.5 mA | 6 | ||
| Leakage current, PWRGD | 1 | µA | VI = 5.5 V | 6 | |||
| Current limit, VI = 6 V, output shorted | 4.5 | 7.5 | A | VI = 6 V, output shorted | 6 | ||
| Current limit total response time | 200 | ns | 6 | ||||
| Thermal shutdown trip point | 135 | 150 | 165 | °C | 6 | ||
| Power MOSFET rDS(on) | rDS(on) | 59 | 88 | mΩ | VI = 6 V | 6 | |
| Power MOSFET rDS(on) | rDS(on) | 136 | mΩ | IO = 3 A, VI = 3 V | 6 | ||
| Thermal shutdown hysteresis | 10 | °C | 6 | ||||
| Junction-to-ambient thermal resistance | RθJA | 26 | °C/W | Test board per footnote (1) of Thermal Information | 4 | ||
| Junction-to-ambient thermal resistance (without solder on PowerPad) | RθJA | 57.5 | °C/W | Without solder on PowerPad | 4 | ||
| UVLO rising and falling edge deglitch | 2.5 | µs | 5 | ||||
| Enable hysteresis voltage, SS/ENA | 0.03 | V | 6 | ||||
| Falling edge deglitch, SS/ENA | 2.5 | µs | 6 | ||||
| Powergood threshold voltage, VSENSE falling | 90 | %Vref | 6 | ||||
| Powergood hysteresis voltage | 3 | %Vref | 6 | ||||
| Powergood falling edge deglitch | 35 | µs | 6 | ||||
| Current limit leading edge blanking time | 100 | ns | 6 |
CAD (KiCad official)
- Symbol:
TPS54316PWP - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps54316pwp-etched.step/tps54316pwp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54316pwp.step/tps54316pwp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (31 pp, sha256
877a5f0bc56ab487, retrieved 2026-10-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).