component

SN74F260N

Public Made by Adom

by adom

Texas Instruments Logic Gates, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74f260nfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

SN74F260N

Texas Instruments · Logic Gates · PDIP-14

SN74F260N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input A of NOR gate 1, which forms Y = A + B + C + D + E in positive logic; VIH min 2 V and VIL max 0.8 V.
2 1B input Data input B of NOR gate 1, which forms Y = A + B + C + D + E in positive logic; VIH min 2 V and VIL max 0.8 V.
3 1C input Data input C of NOR gate 1, which forms Y = A + B + C + D + E in positive logic; VIH min 2 V and VIL max 0.8 V.
4 2A input Data input A of NOR gate 2, which forms Y = A + B + C + D + E in positive logic; VIH min 2 V and VIL max 0.8 V.
5 1Y output Output of NOR gate 1; recommended IOL max 20 mA and IOH min -1 mA.
6 2Y output Output of NOR gate 2; recommended IOL max 20 mA and IOH min -1 mA.
7 GND power_in Ground reference pin of the device.
8 2B input Data input B of NOR gate 2, which forms Y = A + B + C + D + E in positive logic; VIH min 2 V and VIL max 0.8 V.
9 2C input Data input C of NOR gate 2, which forms Y = A + B + C + D + E in positive logic; VIH min 2 V and VIL max 0.8 V.
10 2D input Data input D of NOR gate 2, which forms Y = A + B + C + D + E in positive logic; VIH min 2 V and VIL max 0.8 V.
11 2E input Data input E of NOR gate 2, which forms Y = A + B + C + D + E in positive logic; VIH min 2 V and VIL max 0.8 V.
12 1D input Data input D of NOR gate 1, which forms Y = A + B + C + D + E in positive logic; VIH min 2 V and VIL max 0.8 V.
13 1E input Data input E of NOR gate 1, which forms Y = A + B + C + D + E in positive logic; VIH min 2 V and VIL max 0.8 V.
14 VCC power_in Supply voltage, recommended 4.5 V to 5.5 V (5 V nominal), with absolute maximum -0.5 V to 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5 5.5 V 2
High-level input voltage VIH 2 V 2
Low-level input voltage VIL 0.8 V 2
Input clamp current IIK -18 mA 2
High-level output current IOH -1 mA 2
Low-level output current IOL 20 mA 2
Operating free-air temperature TA 0 70 °C 2
Supply voltage range VCC -0.5 7 V 1
Input voltage range VI -1.2 7 V See Note 1 1
Input current range -30 5 mA 1
Voltage applied to any output in the high state -0.5 V 1
Current into any output in the low state 40 mA 1
Operating free-air temperature range 0 70 °C 1
Storage temperature range -65 150 °C 1
Input clamp voltage VIK -1.2 V VCC = 4.5 V, II = -18 mA 2
High-level output voltage VOH 2.5 3.4 V VCC = 4.5 V, IOH = -1 mA 2
High-level output voltage VOH 2.7 V VCC = 4.75 V, IOH = -1 mA 2
Low-level output voltage VOL 0.3 0.5 V VCC = 4.5 V, IOL = 20 mA 2
Input current at maximum input voltage II 0.1 mA VCC = 5.5 V, VI = 7 V 2
High-level input current IIH 20 µA VCC = 5.5 V, VI = 2.7 V 2
Low-level input current IIL -0.6 mA VCC = 5.5 V, VI = 0.5 V 2
Short-circuit output current IOS -60 -150 mA VCC = 5.5 V, VO = 0 2
Supply current, outputs high ICCH 4.6 6.5 mA VCC = 5.5 V, VI = 0 2
Supply current, outputs low ICCL 7.3 9.5 mA VCC = 5.5 V, VI = 4.5 V 2
Propagation delay, low-to-high (ABCDE to Y) tPLH 1.7 4 5.5 ns VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C 2
Propagation delay, low-to-high (ABCDE to Y) tPLH 1.2 6.5 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 2
Propagation delay, high-to-low (A, B, C, D, E to Y) tPHL 1 2.5 4 ns VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C 2
Propagation delay, high-to-low (A, B, C, D, E to Y) tPHL 1 4.5 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 2

CAD (KiCad official)

  • Symbol: SN74F260N
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74f260n-etched.step / sn74f260n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74f260n.step / sn74f260n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (11 pp, sha256 e45aaf2307dd3ddb, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF