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TPS7A8901RTJR

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by Ray

Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, QFN-20-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

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TPS7A8901RTJR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · QFN-20-EP(4x4)

TPS7A8901RTJR from Texas Instruments, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN1 power_in Input supply pin for LDO 1. A 10 μF or greater input capacitor is required, placed as close to the input as possible. Input voltage range 1.4 V to 6.5 V.
2 IN1 power_in Input supply pin for LDO 1 (second connection). Tie to pin 1. A 10 μF or greater input capacitor is required.
3 GND power_in Ground pin. Must be connected to ground, the thermal pad, and pin 13 with a low-impedance connection.
4 IN2 power_in Input supply pin for LDO 2. A 10 μF or greater input capacitor is required, placed as close to the input as possible. Input voltage range 1.4 V to 6.5 V.
5 IN2 power_in Input supply pin for LDO 2 (second connection). Tie to pin 4. A 10 μF or greater input capacitor is required.
6 EN2 input Enable pin for LDO 2. VEN ≥ VIH(EN) enables the regulator; VEN ≤ VIL(EN) disables it. Must be connected to IN2 if the enable function is not used.
7 NR/SS2 passive Noise-reduction and soft-start pin for LDO 2. An external capacitor between this pin and ground reduces reference voltage noise and enables the soft-start function. A 10 nF or larger capacitor is recommended (up to 1 μF).
8 SS_CTRL2 input Soft-start control pin for LDO 2. Connect either to GND or IN2 to allow normal or fast charging of the NR/SS2 capacitor. Tie to GND to avoid output overshoot if SS_CTRL2 is not used.
9 PG2 output Open-drain power-good indicator pin for LDO 2. Requires a 10 kΩ to 100 kΩ external pull-up resistor. May be left floating or connected to GND if unused.
10 FB2 input Feedback pin for LDO 2, connected to the error amplifier. A 10 nF feed-forward capacitor from FB2 to OUT2 (as close to the device as possible) is recommended to maximize ac performance, though not required.
11 OUT2 power_out Regulated output for LDO 2. A 22 μF or greater ceramic capacitor (10 μF or greater effective capacitance) from OUT2 to ground is required for stability, placed as close to the output as possible. Output voltage range 0.8 V to 5.2 V, up to 2 A.
12 OUT2 power_out Regulated output for LDO 2 (second connection). Tie to pin 11.
13 GND power_in Ground pin. Must be connected to ground, the thermal pad, and pin 3 with a low-impedance connection.
14 OUT1 power_out Regulated output for LDO 1. A 22 μF or greater ceramic capacitor (10 μF or greater effective capacitance) from OUT1 to ground is required for stability, placed as close to the output as possible. Output voltage range 0.8 V to 5.2 V, up to 2 A.
15 OUT1 power_out Regulated output for LDO 1 (second connection). Tie to pin 14.
16 FB1 input Feedback pin for LDO 1, connected to the error amplifier. A 10 nF feed-forward capacitor from FB1 to OUT1 (as close to the device as possible) is recommended to maximize ac performance, though not required.
17 PG1 output Open-drain power-good indicator pin for LDO 1. Requires a 10 kΩ to 100 kΩ external pull-up resistor. May be left floating or connected to GND if unused.
18 SS_CTRL1 input Soft-start control pin for LDO 1. Connect either to GND or IN1 to allow normal or fast charging of the NR/SS1 capacitor. Tie to GND to avoid output overshoot if SS_CTRL1 is not used.
19 NR/SS1 passive Noise-reduction and soft-start pin for LDO 1. An external capacitor between this pin and ground reduces reference voltage noise and enables the soft-start function. A 10 nF or larger capacitor is recommended (up to 1 μF).
20 EN1 input Enable pin for LDO 1. VEN ≥ VIH(EN) enables the regulator; VEN ≤ VIL(EN) disables it. Must be connected to IN1 if the enable function is not used.
21 GND power_in Thermal pad. Must be connected to a large-area ground plane. Internally connected to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-20-EP(4x4)
Category PMIC
Pins 21

Ordering variants

Same part, different packaging or reel option.

  • TPS7A8901RTJR
  • TPS7A8901RTJRRTJT

CAD (KiCad official)

  • Symbol: TPS7A8901RTJR
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tps7a8901rtjr.step 230 KB You want the bare part, or you mark your own boards.
tps7a8901rtjr-etched.step 2.6 MB You want the part with TPS7A8901RTJR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 644 faces against 134 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 37b4273301683e12, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF