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IS25LP064A-JBLA3-TR
Public Made by Adomby adom
ISSI Integrated Silicon Solution NOR FLASH, SOIC-8-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownIS25LP064A-JBLA3-TR
ISSI Integrated Silicon Solution · NOR FLASH · SOIC-8-208mil
IS25LP064A-JBLA3-TR from ISSI Integrated Silicon Solution, in a SOIC-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CE# | input | Chip Enable input: when driven high the device is deselected and outputs are high impedance, and after power-up CE# must transition from high to low before a new instruction is accepted. |
| 2 | SO (IO1) | bidirectional | Serial Data Output in standard SPI, read on the falling edge of SCK, and becomes bidirectional IO1 in Dual and Quad SPI modes. |
| 3 | WP# (IO2) | bidirectional | Write Protect input that, with the SRWD bit set to 1 and WP# pulled low, write-protects the Status Register; when QE is set to 1 it is used as IO2 and the WP# function is not available. |
| 4 | GND | power_in | Ground: connect to ground when referenced to Vcc. |
| 5 | SI (IO0) | bidirectional | Serial Data Input in standard SPI, latched on the rising edge of SCK, and becomes bidirectional IO0 in Dual and Quad SPI modes. |
| 6 | SCK | input | Serial Data Clock: synchronized clock for input and output timing operations. |
| 7 | HOLD# (IO3) | bidirectional | Active-low HOLD input that pauses serial communication while CE# is low (SO goes high impedance) without resetting the sequence; becomes IO3 when QE is set to 1, and is HOLD# by default (P7=0) on this standard-pinout part. |
| 8 | Vcc | power_in | Power: device core power supply. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ISSI Integrated Silicon Solution |
| Package | SOIC-8-208mil |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC Power Supply | VCC | 2.7 | 3 | 3.6 | V | Max. 133MHz | 81 |
| VCC Power Supply | VCC | 2.3 | 3 | 3.6 | V | Max. 104MHz | 81 |
| Operating Temperature (Automotive Grade A3) | -40 | 125 | °C | Automotive Grade A3 | 81 | ||
| Storage Temperature | -65 | 150 | °C | 81 | |||
| Surface Mount Lead Soldering Temperature | 260 | °C | Lead-free package, 3 seconds | 81 | |||
| Input Voltage with Respect to Ground on All Pins | -0.5 | V | Max = VCC + 0.5V | 81 | |||
| All Output Voltage with Respect to Ground | -0.5 | V | Max = VCC + 0.5V | 81 | |||
| VCC Supply Voltage (absolute maximum) | VCC | -0.5 | 6 | V | 81 | ||
| Electrostatic Discharge Voltage (Human Body Model) | -2000 | 2000 | V | ANSI/ESDA/JEDEC JS-001 | 81 | ||
| VCC Active Read Current (NORD) | ICC1 | 5 | 9 | mA | NORD at 50MHz | 82 | |
| VCC Active Read Current (FRD Single) | ICC1 | 7 | 11 | mA | FRD Single at 133MHz | 82 | |
| VCC Active Read Current (FRD Quad) | ICC1 | 10 | 14 | mA | FRD Quad at 133MHz | 82 | |
| VCC Program Current | ICC2 | 25 | mA | CE# = VCC, 125°C | 82 | ||
| VCC WRSR Current | ICC3 | 25 | mA | CE# = VCC, 125°C | 82 | ||
| VCC Erase Current (SER/BER32K/BER64K) | ICC4 | 25 | mA | CE# = VCC, 125°C | 82 | ||
| VCC Erase Current (CE) | ICC5 | 25 | mA | CE# = VCC, 125°C | 82 | ||
| VCC Standby Current CMOS | ISB1 | 60 | µA | VCC = VMAX, CE# = VCC, 125°C | 82 | ||
| Deep Power Down Current | ISB2 | 30 | µA | VCC = VMAX, CE# = VCC, 125°C | 82 | ||
| Input Leakage Current | ILI | -1 | 1 | µA | CE# = VCC, RESET#(4) = VCC | 82 | |
| Output Leakage Current | ILO | -1 | 1 | µA | CE# = VCC, RESET#(4) = VCC | 82 | |
| Input Low Voltage | VIL | -0.5 | V | 82 | |||
| Output Low Voltage | VOL | 0.2 | V | VMIN < VCC < VMAX, IOL = 100 µA | 82 | ||
| Input Capacitance (CE#, SCK) | CIN | 6 | pF | VIN = 0V | 83 | ||
| Input/Output Capacitance (other pins) | CIN/OUT | 8 | pF | VIN/OUT = 0V | 83 | ||
| Input Rise and Fall Times | TR,TF | 5 | ns | 83 | |||
| Clock Frequency for fast read mode (SPI, Dual, Dual I/O, Quad I/O, QPI) | fCT | 0 | 133 | MHz | Vcc=2.7V~3.6V | 84 | |
| Clock Frequency for fast read mode (SPI, Dual, Dual I/O, Quad I/O, QPI) | fCT | 0 | 104 | MHz | Vcc=2.3V~3.6V | 84 | |
| Clock Frequency for read mode SPI | fC | 0 | 50 | MHz | 84 | ||
| SCK Rise Time (peak to peak) | tCLCH | 0.1 | V/ns | 84 | |||
| SCK Fall Time (peak to peak) | tCHCL | 0.1 | V/ns | 84 | |||
| CE# High Time | tCEH | 7 | ns | 84 | |||
| CE# Setup Time | tCS | 6 | ns | 84 | |||
| CE# Hold Time | tCH | 6 | ns | 84 | |||
| Data In Setup Time | tDS | 2 | ns | Normal Mode | 84 | ||
| Data In Hold Time | tDH | 2 | ns | Normal Mode | 84 | ||
| Output Valid | tV | 7 | ns | @133MHz (CL = 15pF) | 84 | ||
| Output Valid | tV | 8 | ns | @104MHz (CL = 30pF) | 84 | ||
| Output Hold Time | tOH | 2 | ns | 84 | |||
| Output Disable Time | tDIS | 8 | ns | 84 | |||
| HOLD Active Setup Time relative to SCK | tHLCH | 5 | ns | 84 | |||
| HOLD Active Hold Time relative to SCK | tCHHH | 5 | ns | 84 | |||
| HOLD Not Active Setup Time relative to SCK | tHHCH | 5 | ns | 84 | |||
| HOLD Not Active Hold Time relative to SCK | tCHHL | 5 | ns | 84 | |||
| HOLD to Output Low Z | tLZ | 12 | ns | 84 | |||
| HOLD to Output High Z | tHZ | 12 | ns | 84 | |||
| Sector Erase Time (4Kbyte) | tEC | 70 | 300 | ms | 84 | ||
| Block Erase Time (32Kbyte) | 0.1 | 0.5 | s | 84 | |||
| Block Erase Time (64Kbyte) | 0.15 | 1 | s | 84 | |||
| Chip Erase Time | 16 | 45 | s | 64Mb | 84 | ||
| Page Program Time | tPP | 0.2 | 0.8 | ms | 84 | ||
| Release Deep Power Down | tRES1 | 3 | µs | 85 | |||
| Deep Power Down | tDP | 3 | µs | 85 | |||
| Write Status Register Time | tW | 2 | 15 | ms | 85 | ||
| Suspend to Read Ready | tSUS | 100 | µs | 85 | |||
| Software Reset Recovery Time | tSRST | 100 | µs | 85 | |||
| Byte Program Time | 8 | 40 | µs | 89 | |||
| VCC(min) to CE# Low | tVCE | 1 | ms | 88 | |||
| Power-up Time Delay to Write Instruction | tPUW | 1 | 10 | ms | 88 | ||
| Write Inhibit Voltage | VWI | 2.1 | V | 88 |
CAD (KiCad official)
- Symbol:
IS25LP064A-JBLA3-TR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8-208mil (KiCad packages3D, STEP)
- 3D model files:
is25lp064a-jbla3-tr-etched.step/is25lp064a-jbla3-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);is25lp064a-jbla3-tr.step/is25lp064a-jbla3-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ISSI Integrated Silicon Solution datasheet (99 pp, sha256
c0f9e25149040c33, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).