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AD7895BRZ-10
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Analog Devices Analog To Digital Converters (ADCs), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD7895BRZ-10
Analog Devices · Analog To Digital Converters (ADCs) · SOIC-8
AD7895BRZ-10 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REF IN | input | Voltage reference input, buffered on chip, with a nominal reference voltage of +2.5 V for correct operation of the AD7895. |
| 2 | VIN | power_in | Analog input channel with an input range of ±10 V (AD7895-10), ±2.5 V (AD7895-3) and 0 V to +2.5 V (AD7895-2). |
| 3 | GND | power_in | Analog ground serving as the ground reference for the track/hold, comparator, digital circuitry and DAC. |
| 4 | SCLK | input | Serial clock input; a new serial data bit is clocked out on its falling edge, data is guaranteed valid for 10 ns after the falling edge, and the clock should be taken low at the end of serial data transmission. |
| 5 | SDATA | output | Serial data output providing sixteen bits (four leading zeros followed by 12 bits of conversion data), which is three-stated after the sixteenth falling edge of SCLK. |
| 6 | BUSY | output | Goes high on the falling edge of CONVST to indicate a conversion is in progress and returns low when the conversion is complete. |
| 7 | CONVST | input | Edge-triggered convert start input; its falling edge puts the track/hold into hold mode and initiates conversion, and if it is low at the end of conversion the part enters power-down, with a rising edge waking the part. |
| 8 | VDD | power_in | Positive supply voltage of +5 V ± 5%. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Data Converters |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy | -1 | 1 | LSB | 2 | |||
| Differential Nonlinearity | -1 | 1 | LSB | 2 | |||
| Positive Full-Scale Error | -2 | 2 | LSB | 2 | |||
| Negative Full-Scale Error | -2 | 2 | LSB | AD7895-10, AD7895-3 only | 2 | ||
| Bipolar Zero Error | -3 | 3 | LSB | AD7895-10, AD7895-3 only | 2 | ||
| Signal to (Noise + Distortion) Ratio | 70 | dB | @ +25°C; fIN = 50 kHz Sine Wave, fSAMPLE = 200 kHz | 2 | |||
| Total Harmonic Distortion | THD | -78 | dB | fIN = 50 kHz Sine Wave, fSAMPLE = 200 kHz | 2 | ||
| Input Voltage Range | -10 | 10 | V | AD7895-10 | 2 | ||
| Input Resistance | 24 | kΩ | AD7895-10 | 2 | |||
| REF IN Input Voltage Range | 2.375 | 2.625 | V | 2.5 V ± 5% | 2 | ||
| Input Current | 1 | µA | REF IN | 2 | |||
| Input Capacitance | 10 | pF | REF IN | 2 | |||
| Input High Voltage | VINH | 2.4 | V | VDD = 5 V ± 5% | 2 | ||
| Input Low Voltage | VINL | 0.8 | V | VDD = 5 V ± 5% | 2 | ||
| Input Current | IIN | -10 | 10 | µA | VIN = 0 V to VDD | 2 | |
| Output High Voltage | VOH | 4 | V | ISOURCE = 200 µA | 2 | ||
| Output Low Voltage | VOL | 0.4 | V | ISINK = 1.6 mA | 2 | ||
| Conversion Time, Mode 1 Operation | 3.8 | µs | 2 | ||||
| Conversion Time, Mode 2 Operation | 9.8 | µs | 2 | ||||
| Track/Hold Acquisition Time | 0.5 | µs | 2 | ||||
| VDD | VDD | 5 | V | nom ±5% for specified performance | 2 | ||
| IDD | IDD | 4 | mA | Digital inputs @ VDD, VDD = 5 V ± 5% | 2 | ||
| Power Dissipation | 20 | mW | 2 | ||||
| Power-Down IDD | IDD | 55 | µA | @ +25°C; digital inputs @ GND, VDD = 5 V ± 5% | 2 | ||
| Power-Down IDD | IDD | 10 | µA | TMIN to TMAX; digital inputs @ GND, VDD = 5 V ± 5% | 2 | ||
| Power Dissipation in Power-Down Mode | 25 | µW | @ +25°C | 2 | |||
| CONVST Pulse Width | t1 | 40 | ns | 3 | |||
| SCLK High Pulse Width | t2 | 352 | ns | 3 | |||
| SCLK Low Pulse Width | t3 | 352 | ns | 3 | |||
| Data Access Time after Falling Edge of SCLK | t4 | 603 | ns | VDD = 5 V ± 5% | 3 | ||
| Data Hold Time after Falling Edge of SCLK | t5 | 10 | ns | 3 | |||
| Bus Relinquish Time after Falling Edge of SCLK | t6 | 504 | ns | 3 | |||
| VDD to GND | VDD | -0.3 | 7 | V | 3 | ||
| Analog Input Voltage to GND | VIN | -17 | 17 | V | AD7895-10 | 3 | |
| Reference Input Voltage to GND | -0.3 | V | Upper limit VDD + 0.3 V (not numeric) | 3 | |||
| Digital Input Voltage to GND | -0.3 | V | Upper limit VDD + 0.3 V (not numeric) | 3 | |||
| Digital Output Voltage to GND | -0.3 | V | Upper limit VDD + 0.3 V (not numeric) | 3 | |||
| Operating Temperature Range | TA | -40 | 85 | °C | Commercial (A, B Versions) | 3 | |
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| Junction Temperature | 150 | °C | 3 | ||||
| SOIC Package Power Dissipation | 450 | mW | 3 | ||||
| θJA Thermal Impedance, SOIC | θJA | 170 | °C/W | SOIC package | 3 | ||
| Lead Temperature, Vapor Phase (60 sec) | 215 | °C | Vapor phase, 60 sec | 3 | |||
| Lead Temperature, Infrared (15 sec) | 220 | °C | Infrared, 15 sec | 3 |
CAD (KiCad official)
- Symbol:
AD7895BRZ-10 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ad7895brz-10-etched.step/ad7895brz-10-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7895brz-10.step/ad7895brz-10.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (12 pp, sha256
912a825739df66ae, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).