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F2800154QRHBRQ1

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TEXAS INSTRUMENTS Global Sourcing Parts, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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F2800154QRHBRQ1

TEXAS INSTRUMENTS · Global Sourcing Parts · VQFN-32-EP(5x5)

F2800154QRHBRQ1 from TEXAS INSTRUMENTS, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XRSn bidirectional Active-low device reset; the internal pullup is always active.
2 A6,C6,GPIO226,GPIO228 bidirectional ADC-A input 6 / ADC-C input 6 shared with GPIO226 and GPIO228; if both GPIOs are configured as outputs, GPIO226 automatically changes to an input to prevent contention on this pin.
3 A3/C5,GPIO242 bidirectional ADC-A input 3 / ADC-C input 5 shared with GPIO242, a general-purpose input/output.
4 A2/C9,GPIO224 bidirectional ADC-A input 2 / ADC-C input 9 shared with GPIO224, a general-purpose input/output.
5 A15/C7,C4/A14 input Analog input shared between ADC-A/ADC-C channels 15 and 7 and channels 4 and 14 (multiple analog channels bonded to this pin).
6 A11/C0,A5/C2 input Analog input shared between ADC-A channel 11 / ADC-C channel 0 and ADC-A channel 5 / ADC-C channel 2.
7 A0/C15/CMP1_DACL,A1 input Analog input shared between ADC-A channels 0 and 1, ADC-C channel 15 and the CMPSS-1 low DAC output CMP1_DACL.
8 A12/C1,A7/C3 input Analog input shared between ADC-A channels 12 and 7 and ADC-C channels 1 and 3.
9 A8/C11 input Analog input shared between ADC-A channel 8 and ADC-C channel 11.
10 VSSA power_in Analog ground.
11 VDDA power_in 3.3-V analog power pin; on the 32-pin QFN package VREFHI is internally tied to VDDA.
12 A4/C14 input Analog input shared between ADC-A channel 4 and ADC-C channel 14.
13 A10/C10,C8/A9,GPIO227,GPIO230 bidirectional Analog input shared between ADC-A channel 10 / ADC-C channel 10 and ADC-C channel 8 / ADC-A channel 9, multiplexed with GPIO227 and GPIO230; if both GPIO227 and GPIO230 are configured as outputs, GPIO227 automatically changes to an input.
14 GPIO11 bidirectional General-purpose input/output 11 with multiplexed peripheral functions per the pin attribute table; internal pullup disabled by default.
15 GPIO24 bidirectional General-purpose input/output 24 with multiplexed peripheral functions per the pin attribute table; internal pullup disabled by default.
16 TCK input JTAG test clock input; the internal pullup is active.
17 GPIO37/TDO bidirectional JTAG test data output (TDO) by default; the pin is tri-stated when there is no JTAG activity and can otherwise be used as GPIO37.
18 TMS input JTAG test mode select; the internal pullup is active and a pullup resistor is recommended.
19 GPIO35/TDI bidirectional JTAG test data input (TDI) by default; the internal pullup is disabled by default and should be enabled or externally pulled up if used as TDI.
20 GPIO32 bidirectional General-purpose input/output 32 with multiplexed peripheral functions per the digital signals table.
21 GPIO18/X2 bidirectional General-purpose input/output 18, or crystal oscillator output X2 when the crystal oscillator is used.
22 GPIO19/X1 bidirectional General-purpose input/output 19, or crystal oscillator / single-ended clock input X1; the initialization software must configure this pin before the crystal oscillator is enabled.
23 VDDIO power_in 3.3-V digital I/O power pin.
24 VDD power_in 1.2-V digital logic power pin.
25 VREGENZ input Internal voltage regulator enable with internal pulldown; tie low to VSS to enable the internal VREG, or tie high to VDDIO to use an external supply.
26 GPIO3 bidirectional General-purpose input/output 3 with multiplexed peripheral functions per the digital signals table.
27 GPIO1 bidirectional General-purpose input/output 1 with multiplexed peripheral functions per the digital signals table.
28 GPIO0 bidirectional General-purpose input/output 0 with multiplexed peripheral functions per the digital signals table.
29 GPIO7 bidirectional General-purpose input/output 7 with multiplexed peripheral functions per the digital signals table.
30 GPIO5 bidirectional General-purpose input/output 5 with multiplexed peripheral functions per the digital signals table.
31 GPIO29 bidirectional General-purpose input/output 29 with multiplexed peripheral functions per the digital signals table.
32 A16/C16,GPIO28 bidirectional ADC-A input 16 / ADC-C input 16 shared with GPIO28, a general-purpose input/output.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer TEXAS INSTRUMENTS
Package VQFN-32-EP(5x5)
Category Global Sourcing Parts
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Low-level output voltage VOL 0.4 V IOL = IOL MAX 59
Low-level output voltage VOL 0.2 V IOL = 100 µA 59
High-level output impedance for all output pins ROH 50 65 96 Ω VOH=VDDS-0.4V 59
Low-level output impedance for all output pins ROL 48 60 84 Ω VOL=0.4V 59
High-level input voltage VIH 2 V 59
Low-level input voltage VIL 0.8 V 59
High-level output source current for all output pins IOH -4 mA 59
Low-level output sink current for all output pins IOL 4 mA 59
Weak pulldown resistance RPULLDOWN 22.66 31.49 61.55 kΩ 59
Weak pullup resistance RPULLUP 19.89 29.45 53.63 kΩ 59
Device supply voltage, VDDIO and VDDA (internal BOR enabled) VDDIO, VDDA 3.3 3.63 V Internal BOR enabled 48
Device supply voltage, VDDIO and VDDA (internal BOR disabled) VDDIO, VDDA 2.8 3.3 3.63 V Internal BOR disabled 48
Device supply voltage, VDD VDD 1.14 1.2 1.32 V 48
Junction temperature, TJ (F280015xQ parts) TJ -40 140 °C F280015xS, F280015xQ parts 48
Free-Air temperature, TA (F280015xQ parts) TA -40 125 °C F280015xS, F280015xQ parts 48
Supply voltage VDD with respect to VSS VDD -0.3 1.5 V with respect to VSS 47
Supply voltage VDDIO with respect to VSS VDDIO -0.3 4.6 V with respect to VSS 47
Supply voltage VDDA with respect to VSSA VDDA -0.3 4.6 V with respect to VSSA 47
Input voltage VIN (3.3 V) -0.3 4.6 V 47
Output voltage VO -0.3 4.6 V 47
Input clamp current - per pin IIK -20 20 mA VIN < VSS/VSSA or VIN > VDDIO/VDDA 47
Input clamp current - total for all pins IIKTOTAL -20 20 mA VIN < VSS/VSSA or VIN > VDDIO/VDDA 47
Output current Digital output (per pin) IOUT -20 20 mA per pin 47
Operating junction temperature TJ -40 155 °C 47
Storage temperature Tstg -65 150 °C 47
Junction-to-case thermal resistance, top RθJC 20.7 °C/W JEDEC 2S2P system (RθJC uses 1S0P) 61
Junction-to-case thermal resistance, bottom RθJC 2.3 °C/W JEDEC 2S2P system (RθJC uses 1S0P) 61
Junction-to-board thermal resistance RθJB 11.3 °C/W JEDEC 2S2P system 61
Junction-to-free air thermal resistance (High k PCB) RθJA 31.2 °C/W JEDEC 2S2P system 61
Junction-to-package top ΨJT 0.2 °C/W JEDEC 2S2P system 61
Junction-to-board ΨJB 11.2 °C/W JEDEC 2S2P system 61
Internal Voltage Regulator Output VVREG 1.152 1.2 1.248 V 71
Input current pins with pulldown IPULLDOWN 120 µA VDDIO = 3.3 V, VIN = VDDIO 59
Input current digital inputs with pullup enabled IPULLUP 160 µA VDDIO = 3.3 V, VIN = 0 V 59
Pin leakage (digital inputs) ILEAK 0.1 µA 0 V ≤ VIN ≤ VDDIO; pullups and outputs disabled 59
Input hysteresis (AIO) VHYSTERESIS 125 mV 59
Input hysteresis (GPIO) VHYSTERESIS 125 mV 59
Input capacitance (digital inputs) CI 2 pF 59

CAD (KiCad official)

  • Symbol: F2800154QRHBRQ1
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: f2800154qrhbrq1-etched.step / f2800154qrhbrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); f2800154qrhbrq1.step / f2800154qrhbrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TEXAS INSTRUMENTS datasheet (252 pp, sha256 e5e9c14e326ac962, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF