Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

SN74HCS365DR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-16

SN74HCS365DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Output enable 1, active low; inhibits all outputs to high-impedance when high
2 A1 input Schmitt-trigger input for channel 1; 0 to VCC with ±100 nA input leakage typical
3 Y1 tri_state 3-state buffered output for channel 1; ±7.8 mA drive at 6 V, high-impedance when OE1 or OE2 high
4 A2 input Schmitt-trigger input for channel 2; 0 to VCC with ±100 nA input leakage typical
5 Y2 tri_state 3-state buffered output for channel 2; ±7.8 mA drive at 6 V, high-impedance when OE1 or OE2 high
6 A3 input Schmitt-trigger input for channel 3; 0 to VCC with ±100 nA input leakage typical
7 Y3 tri_state 3-state buffered output for channel 3; ±7.8 mA drive at 6 V, high-impedance when OE1 or OE2 high
8 GND power_in Ground; 0 V reference
9 Y4 tri_state 3-state buffered output for channel 4; ±7.8 mA drive at 6 V, high-impedance when OE1 or OE2 high
10 A4 input Schmitt-trigger input for channel 4; 0 to VCC with ±100 nA input leakage typical
11 Y5 tri_state 3-state buffered output for channel 5; ±7.8 mA drive at 6 V, high-impedance when OE1 or OE2 high
12 A5 input Schmitt-trigger input for channel 5; 0 to VCC with ±100 nA input leakage typical
13 Y6 tri_state 3-state buffered output for channel 6; ±7.8 mA drive at 6 V, high-impedance when OE1 or OE2 high
14 A6 input Schmitt-trigger input for channel 6; 0 to VCC with ±100 nA input leakage typical
15 OE2 input Output enable 2, active low; inhibits all outputs to high-impedance when high
16 VCC power_out Positive supply; 2 to 6 V operating range

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74HCS365DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hcs365dr-etched.step / sn74hcs365dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hcs365dr.step / sn74hcs365dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 952cb19381170a2f, retrieved 2026-09-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF