component
AT24C02N
Public Made by Adomby adom
HGSEMI EEPROM, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAT24C02N
HGSEMI · EEPROM · DIP-8
AT24C02N from HGSEMI, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | E0 | input | Slave address setting input (device address bit E0); internally pulled down to Vss if left floating. |
| 2 | E1 | input | Slave address setting input (device address bit E1); internally pulled down to Vss if left floating. |
| 3 | E2 | input | Slave address setting input (device address bit E2); internally pulled down to Vss if left floating, allowing up to 8 devices on one bus. |
| 4 | Vss | power_in | Ground, the reference for the VCC supply voltage. |
| 5 | SDA | bidirectional | Serial data input and output; open-drain driven and may be wire-OR'ed with other open-drain or open-collector devices. |
| 6 | SCL | input | Serial clock input that clocks data in on the positive edge and out on the negative edge. |
| 7 | WCB | input | Write control, low enables write; connected to VCC it inhibits all writes to the memory, and it is internally pulled down to Vss if left floating. |
| 8 | VCC | power_in | Supply voltage, 1.7V to 5.5V operating range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | DIP-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature range | TA | -40 | 125 | °C | 4 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 4 | ||
| Supply Voltage | VCC | -0.5 | 6.5 | V | 4 | ||
| Input or output range | VIO | -0.5 | 6.5 | V | 4 | ||
| DC output current (SDA=0) | IOL | 5 | mA | SDA=0 | 4 | ||
| Lead Temperature (Soldering, 10 seconds) | TL | 260 | °C | Soldering, 10 seconds | 4 | ||
| Input / Output Capacitance (SDA) | CI/O | 8 | pF | VI/O= Vss | 4 | ||
| Input Capacitance (E0, E1,E2,WCB,SCL) | CIN | 6 | pF | VIN= Vss | 4 | ||
| Supply Voltage | Vcc | 1.7 | 5.5 | V | 4 | ||
| Standby Current | Isb | 1 | uA | Vcc = 3.3V | 4 | ||
| Standby Current | Isb | 3 | uA | Vcc = 5.5V | 4 | ||
| Supply Current | ICC1 | 0.2 | 0.4 | mA | Vcc=5.5V, Read at 400khz | 4 | |
| Supply Current | ICC2 | 0.8 | 1.6 | mA | Vcc=5.5V, Write at 400khz | 4 | |
| Input Leakage Current | ILI | 0.1 | 1 | µA | VIN = VCC or Vss | 4 | |
| Output Leakage Current | ILO | 0.05 | 1 | µA | VOUT = VCC or Vss | 4 | |
| Input Low Level | VIL | -0.5 | V | 4 | |||
| Output Low Level | VOL1 | 0.2 | V | VCC = 1.7V (SDA), IOL = 0.15 mA | 4 | ||
| Output Low Level | VOL2 | 0.4 | V | VCC = 3.0V (SDA), IOL = 2.1 mA | 4 | ||
| Clock Frequency, SCL | fSCL | 100 | kHz | 1.7≤VCC≤5.5, CL=100pF | 5 | ||
| Clock Low to Data Out Valid | tAA | 0.05 | 3.45 | µs | 1.7≤VCC≤5.5, CL=100pF | 5 | |
| Time the bus must be free before a new transmission can start | tBUF | 4.7 | µs | 1.7≤VCC≤5.5, CL=100pF | 5 | ||
| Write Cycle Time | tWR | 5 | ms | 1.7≤VCC≤5.5, CL=100pF | 5 | ||
| Clock Frequency, SCL | fSCL | 400 | kHz | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| Clock Frequency, SCL | fSCL | 1000 | kHz | 1.7≤VCC≤5.5, CL=100pF; second column set (1MHz) | 6 | ||
| Clock Pulse Width Low | tLOW | 1.3 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| Clock Pulse Width Low | tLOW | 0.4 | µs | 1.7≤VCC≤5.5, CL=100pF; second column set (1MHz) | 6 | ||
| Clock Pulse Width High | tHIGH | 0.6 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| Clock Pulse Width High | tHIGH | 0.4 | µs | 1.7≤VCC≤5.5, CL=100pF; second column set (1MHz) | 6 | ||
| Clock Low to Data Out Valid | tAA | 0.05 | 0.9 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | |
| Clock Low to Data Out Valid | tAA | 0.05 | 0.55 | µs | 1.7≤VCC≤5.5, CL=100pF; second column set (1MHz) | 6 | |
| Noise Suppression Time | tI | 0.1 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| Noise Suppression Time | tI | 0.05 | µs | 1.7≤VCC≤5.5, CL=100pF; second column set (1MHz) | 6 | ||
| Time the bus must be free before a new transmission can start | tBUF | 1.3 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| Time the bus must be free before a new transmission can start | tBUF | 0.5 | µs | 1.7≤VCC≤5.5, CL=100pF; second column set (1MHz) | 6 | ||
| Start Hold Time | tHD.STA | 0.6 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| Start Hold Time | tHD.STA | 0.25 | µs | 1.7≤VCC≤5.5, CL=100pF; second column set (1MHz) | 6 | ||
| Start Setup Time | tSU.STA | 0.6 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| Start Setup Time | tSU.STA | 0.25 | µs | 1.7≤VCC≤5.5, CL=100pF; second column set (1MHz) | 6 | ||
| Data In Hold Time | tHD.DAT | 0 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| Data In Setup Time | tSU.DAT | 0.1 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| Inputs Rise Time | tR | 0.3 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| Inputs Fall Time | tF | 0.3 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| Inputs Fall Time | tF | 0.1 | µs | 1.7≤VCC≤5.5, CL=100pF; second column set (1MHz) | 6 | ||
| Stop Setup Time | tSU.STO | 0.6 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| Stop Setup Time | tSU.STO | 0.25 | µs | 1.7≤VCC≤5.5, CL=100pF; second column set (1MHz) | 6 | ||
| Data Out Hold Time | tDH | 0.05 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| WCB pin Setup Time | tSU.WCB | 1.2 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| WCB pin Setup Time | tSU.WCB | 0.6 | µs | 1.7≤VCC≤5.5, CL=100pF; second column set (1MHz) | 6 | ||
| WCB pin Hold Time | tHD.WCB | 1.2 | µs | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| WCB pin Hold Time | tHD.WCB | 0.6 | µs | 1.7≤VCC≤5.5, CL=100pF; second column set (1MHz) | 6 | ||
| Write Cycle Time | tWR | 5 | ms | 1.7≤VCC≤5.5, CL=100pF; first column set (400kHz) | 6 | ||
| VCC voltage needed to below VPWD for ensuring initialization will occur | VPWD | 0.7 | V | 8 | |||
| The minimum duration for ensuring initialization will occur | tPWD | 300 | us | 8 | |||
| VCC(min.) to device operation | tVSL | 70 | us | 8 | |||
| VCC Rise Time | tVR | 1 | 500000 | us/V | 8 |
CAD (KiCad official)
- Symbol:
AT24C02N - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
at24c02n-etched.step/at24c02n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at24c02n.step/at24c02n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (18 pp, sha256
14a1ed1066ebdfb3, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).