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AD5755-1ACPZ

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Analog Devices Pre-ordered Chips, LFCSP-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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AD5755-1ACPZ

Analog Devices · Pre-ordered Chips · LFCSP-64(9x9)

AD5755-1ACPZ from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RSET_B passive An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_B temperature drift performance.
2 RSET_A passive An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_A temperature drift performance.
3 REFGND power_in Ground reference point for the internal reference.
4 REFGND power_in Ground reference point for the internal reference.
5 AD0 input Address decode for the device under test on the board.
6 AD1 input Address decode for the device under test on the board; it is not recommended to tie both AD1 and AD0 low when using PEC.
7 SYNC input Active low frame synchronization input for the serial interface; data is transferred in on the falling edge of SCLK while SYNC is low.
8 SCLK input Serial clock input, with data clocked into the input shift register on the falling edge; operates at clock speeds of up to 30 MHz.
9 SDIN input Serial data input; data must be valid on the falling edge of SCLK.
10 SDO output Serial data output used to clock data from the serial register in readback mode.
11 DVDD power_in Digital supply with a voltage range from 2.7 V to 5.5 V.
12 DGND power_in Digital ground.
13 LDAC input Active low load DAC input that updates the DAC outputs; it must not be left unconnected.
14 CLEAR input Active high, edge sensitive input that sets the output to the preprogrammed clear code; the DAC output register cannot be written while CLEAR is active.
15 ALERT output Active high output asserted when there has been no SPI activity on the interface pins for a predetermined time.
16 FAULT output Active low open-drain output asserted for an open circuit in current mode, a short circuit in voltage mode, a PEC error, or an overtemperature.
17 POC input Power-on condition pin read at power-on or after reset; POC = 0 powers up the outputs tristated and POC = 1 applies a 30 kΩ pull-down to ground on the voltage output channel.
18 RESET input Hardware reset active low input.
19 AVDD power_in Positive analog supply with a voltage range from 9 V to 33 V.
20 COMPLV_A passive Optional compensation capacitor connection for the VOUT_A output buffer; a 220 pF capacitor to VOUT_A allows the voltage output to drive up to 2 µF.
21 CHARTA passive HART input connection for DAC Channel A; leave as an open circuit if unused.
22 +VSENSE_A passive Sense connection for the positive voltage output load connection for VOUT_A.
23 COMPDCDC_A passive DC-to-DC compensation capacitor pin; connect a 10 nF capacitor from this pin to ground.
24 VBOOST_A power_in Supply for the Channel A current output stage, also supplying the VOUT_x stage which is regulated to 15 V by the dc-to-dc converter.
25 VOUT_A output Buffered analog output voltage for DAC Channel A.
26 IOUT_A output Current output pin for DAC Channel A.
27 AVSS power_in Negative analog supply with a voltage range from 0 V to −26.4 V.
28 COMPLV_B passive Optional compensation capacitor connection for the VOUT_B output buffer; a 220 pF capacitor to VOUT_B allows the voltage output to drive up to 2 µF.
29 CHARTB passive HART input connection for DAC Channel B; leave as an open circuit if unused.
30 +VSENSE_B passive Sense connection for the positive voltage output load connection for VOUT_B.
31 VOUT_B output Buffered analog output voltage for DAC Channel B.
32 COMPDCDC_B passive DC-to-DC compensation capacitor pin; connect a 10 nF capacitor from this pin to ground.
33 IOUT_B output Current output pin for DAC Channel B.
34 VBOOST_B power_in Supply for the Channel B current output stage, also supplying the VOUT_x stage which is regulated to 15 V by the dc-to-dc converter.
35 AGND power_in Ground reference point for analog circuitry; this must be connected to 0 V.
36 SWB output Switching output for Channel B dc-to-dc circuitry; connect as shown in Figure 81 to use the dc-to-dc feature.
37 GNDSWB power_in Ground connection for the dc-to-dc switching circuit; this pin must always be connected to ground.
38 GNDSWA power_in Ground connection for the dc-to-dc switching circuit; this pin must always be connected to ground.
39 SWA output Switching output for Channel A dc-to-dc circuitry; connect as shown in Figure 81 to use the dc-to-dc feature.
40 AVSS power_in Negative analog supply pin with a voltage range from −10.8 V to −26.4 V; it can be connected to 0 V in unipolar supply mode.
41 SWD output Switching output for Channel D dc-to-dc circuitry; connect as shown in Figure 81 to use the dc-to-dc feature.
42 GNDSWD power_in Ground connection for the dc-to-dc switching circuit; this pin must always be connected to ground.
43 GNDSWC power_in Ground connection for the dc-to-dc switching circuit; this pin must always be connected to ground.
44 SWC output Switching output for Channel C dc-to-dc circuitry; connect as shown in Figure 81 to use the dc-to-dc feature.
45 AVCC power_in Supply for the dc-to-dc circuitry.
46 VBOOST_C power_in Supply for the Channel C current output stage, also supplying the VOUT_x stage which is regulated to 15 V by the dc-to-dc converter.
47 IOUT_C output Current output pin for DAC Channel C.
48 COMPDCDC_C passive DC-to-DC compensation capacitor pin; connect a 10 nF capacitor from this pin to ground.
49 VOUT_C output Buffered analog output voltage for DAC Channel C.
50 +VSENSE_C passive Sense connection for the positive voltage output load connection for VOUT_C.
51 CHARTC passive HART input connection for DAC Channel C; leave as an open circuit if unused.
52 COMPLV_C passive Optional compensation capacitor connection for the VOUT_C output buffer; a 220 pF capacitor to VOUT_C allows the voltage output to drive up to 2 µF.
53 AVSS power_in Negative analog supply pin.
54 IOUT_D output Current output pin for DAC Channel D.
55 VOUT_D output Buffered analog output voltage for DAC Channel D.
56 VBOOST_D power_in Supply for the Channel D current output stage, also supplying the VOUT_x stage which is regulated to 15 V by the dc-to-dc converter.
57 COMPDCDC_D passive DC-to-DC compensation capacitor pin; connect a 10 nF capacitor from this pin to ground.
58 +VSENSE_D passive Sense connection for the positive voltage output load connection for VOUT_D.
59 CHARTD passive HART input connection for DAC Channel D; leave as an open circuit if unused.
60 COMPLV_D passive Optional compensation capacitor connection for the VOUT_D output buffer; a 220 pF capacitor to VOUT_D allows the voltage output to drive up to 2 µF.
61 REFIN input External reference voltage input; REFOUT must be connected to REFIN to use the internal reference.
62 REFOUT output Internal reference voltage output; place a 0.1 µF capacitor between REFOUT and REFGND.
63 RSET_D passive An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_D temperature drift performance.
64 RSET_C passive An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_C temperature drift performance.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-64(9x9)
Category Interface ICs
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD, VBOOST_x to AGND, DGND -0.3 33 V 12
AVSS to AGND, DGND -28 0.3 V 12
AVDD to AVSS -0.3 60 V 12
AVCC to AGND -0.3 7 V 12
DVDD to DGND -0.3 7 V 12
Operating Temperature Range (TA) Industrial TA -40 105 °C 12
Storage Temperature Range -65 150 °C 12
Junction Temperature (TJ max) TJ 125 °C 12
Thermal Impedance 64-Lead LFCSP θJA 28 °C/W Based on a JEDEC 4-layer test board 12
SCLK cycle time t1 50 ns 9
SCLK high time t2 17 ns 9
SYNC falling edge to SCLK falling edge setup time t4 20 ns 9
24th/32nd SCLK falling edge to SYNC rising edge t5 15 ns 9
Data hold time t8 10 ns 9
LDAC falling edge to DAC output response time t11 520 ns 9
SCLK rising edge to SDO valid t15 45 ns 9
AVDD supply voltage AVDD 9 33 V 7
AVSS supply voltage AVSS -26.4 V Maximum printed as −10.8/0 V 7
DVDD supply voltage DVDD 2.7 5.5 V 7
AVCC supply voltage AVCC 4.5 5.5 V 7
AIDD supply current AIDD 8.6 10.5 mA Voltage output mode on all channels, output unloaded, over supplies 8
AIDD supply current AIDD 7 7.5 mA Current output mode on all channels 8
AISS supply current AISS -11 -8.8 mA Voltage output mode on all channels, output unloaded, over supplies 8
AISS supply current AISS -1.7 mA Current output mode on all channels 8
DICC supply current DICC 4 6 mA VIH = DVDD, VIL = DGND, internal oscillator running, over supplies 8
AICC supply current AICC 1 mA Output unloaded, over supplies 8
Power Dissipation 173 mW AVDD = +15 V, AVSS = −15 V, dc-to-dc converter enable, current output mode, outputs disabled 8
VIH, Input High Voltage VIH 2 V 7
VIL, Input Low Voltage VIL 0.8 V 7
VOL, Output Low Voltage (SDO, ALERT) VOL 0.4 V Sinking 200 µA 7
Reference Input Voltage 4.95 5 5.05 V For specified performance 7
Reference Output Voltage 4.995 5 5.005 V TA = 25°C 7
Reference TC -10 5 10 ppm/°C 7
Oscillator Frequency 11.5 13 14.5 MHz This oscillator is divided down to give the dc-to-dc converter switching frequency 7
Total Unadjusted Error (TUE) TUE -0.04 0.04 % FSR AVSS = −15 V, loaded and unloaded 5
Total Unadjusted Error (TUE) TUE -0.03 0.0032 0.03 % FSR TA = 25°C 5
Relative Accuracy (INL) INL -0.006 0.0012 0.006 % FSR 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V ranges 5
Relative Accuracy (INL) on overranges INL -0.008 0.0012 0.008 % FSR On overranges 5
Differential Nonlinearity (DNL) DNL -1 1 LSB Guaranteed monotonic 5
Zero-Scale Error -0.03 0.002 0.03 % FSR 5
Zero-Scale TC -2 2 ppm FSR/°C 5
Offset Error -0.03 0.002 0.03 % FSR 5
Offset TC -2 2 ppm FSR/°C 5
Gain Error -0.03 0.004 0.03 % FSR 5
Gain TC -3 3 ppm FSR/°C 5
Full-Scale Error -0.03 0.002 0.03 % FSR 5
Full-Scale TC -2 2 ppm FSR/°C 5
Total Unadjusted Error (TUE) unipolar supply TUE -0.06 0.025 0.06 % FSR AVSS = 0 V 5
Relative Accuracy (INL) unipolar supply INL -0.009 0.009 % FSR AVSS = 0 V 5
Offset Error unipolar supply -0.07 0.025 0.07 % FSR AVSS = 0 V 5
Gain Error unipolar supply -0.07 0.015 0.07 % FSR AVSS = 0 V 5
Full-Scale Error unipolar supply -0.06 0.015 0.06 % FSR AVSS = 0 V 5
Headroom 1 2.2 V With respect to VBOOST supply 5
Footroom 0.7 1.4 V With respect to the AVSS supply, bipolar output ranges 5
Total Unadjusted Error (TUE) external RSET TUE -0.05 0.009 0.05 % FSR ACCURACY (EXTERNAL RSET), assumes ideal resistor 6
Offset Error external RSET -0.05 0.005 0.05 % FSR ACCURACY (EXTERNAL RSET) 6
Gain Error external RSET -0.05 0.004 0.05 % FSR ACCURACY (EXTERNAL RSET) 6
Full-Scale Error external RSET -0.05 0.008 0.05 % FSR ACCURACY (EXTERNAL RSET) 6
Total Unadjusted Error (TUE) internal RSET TUE -0.14 0.14 % FSR ACCURACY (INTERNAL RSET) 6
Total Unadjusted Error (TUE) internal RSET TUE -0.11 0.009 0.11 % FSR TA = 25°C 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper EPAD Exposed Pad. Connect this exposed pad to the potential of the AVSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper pla 15

CAD (KiCad official)

  • Symbol: AD5755-1ACPZ
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: ad5755-1acpz-etched.step / ad5755-1acpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5755-1acpz.step / ad5755-1acpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (50 pp, sha256 98c402eed9506091, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF