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CY8C4024LQI-S402

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Infineon/Cypress Semicon Microcontrollers (MCU/MPU/SOC), QFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscy8c4024lqi-s402factory-2.0.0extractor-text

Verified CY8C4024LQI-S402

by Ray · last 12 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

12 Nov 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY8C4024LQI-S402 · QFN-32(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 58-page datasheet
  • ✓distributor: lcsc C5651646, digikey 448-CY8C4024LQI-S402-ND, mouser 727-CY8C4024LQI-S402
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-0db63lu1/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.47)
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 39 kB, viewers/symbol.html 24 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy8c4024lqi-s402.kicad_sym✓ cy8c4024lqi-s402.kicad_mod✓ cy8c4024lqi-s402.step
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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CY8C4024LQI-S402

Infineon/Cypress Semicon · Microcontrollers (MCU/MPU/SOC) · QFN-32(5x5)

CY8C4024LQI-S402 from Infineon/Cypress Semicon, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.7 bidirectional Port 1 GPIO bit 7 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and interrupt capability.
2 P2.0 bidirectional Port 2 GPIO bit 0 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM and SCB alternate functions listed in Table 2.
3 P2.1 bidirectional Port 2 GPIO bit 1 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM and SCB alternate functions listed in Table 2.
4 P2.2 bidirectional Port 2 GPIO bit 2 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O and SCB alternate functions listed in Table 2.
5 P2.3 bidirectional Port 2 GPIO bit 3 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O and SCB alternate functions listed in Table 2.
6 P2.5 bidirectional Port 2 GPIO bit 5 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM and SCB alternate functions listed in Table 2.
7 P2.6 bidirectional Port 2 GPIO bit 6 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM and SCB alternate functions listed in Table 2.
8 P2.7 bidirectional Port 2 GPIO bit 7 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM, LPCOMP and SCB alternate functions listed in Table 2.
9 P3.0 bidirectional Port 3 GPIO bit 0 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM and SCB alternate functions listed in Table 2.
10 P3.1 bidirectional Port 3 GPIO bit 1 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM and SCB alternate functions listed in Table 2.
11 P3.2 bidirectional Port 3 GPIO bit 2 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM, SCB and SWD data alternate functions listed in Table 2.
12 P3.3 bidirectional Port 3 GPIO bit 3 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM, SCB and SWD clock alternate functions listed in Table 2.
13 P4.0 bidirectional Port 4 GPIO bit 0 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the CSD VREF_EXT, TCPWM and SCB alternate functions listed in Table 2.
14 P4.1 bidirectional Port 4 GPIO bit 1 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the CSD CSHIELDPADS, TCPWM and SCB alternate functions listed in Table 2.
15 P4.2 bidirectional Port 4 GPIO bit 2 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the CSD CMODPAD, LPCOMP and SCB alternate functions listed in Table 2.
16 P4.3 bidirectional Port 4 GPIO bit 3 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the CSD CSH_TANK, LPCOMP and SCB alternate functions listed in Table 2.
17 P0.0 bidirectional Port 0 GPIO bit 0 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the LPCOMP positive input 0 and TCPWM/SCB alternate functions listed in Table 2.
18 P0.1 bidirectional Port 0 GPIO bit 1 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the LPCOMP negative input 0 and TCPWM/SCB alternate functions listed in Table 2.
19 P0.2 bidirectional Port 0 GPIO bit 2 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the LPCOMP positive input 1 and SCB alternate functions listed in Table 2.
20 P0.3 bidirectional Port 0 GPIO bit 3 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the LPCOMP negative input 1 alternate function listed in Table 2.
21 P0.4 bidirectional Port 0 GPIO bit 4 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the WCO input (wco_in) and SCB alternate functions listed in Table 2.
22 P0.5 bidirectional Port 0 GPIO bit 5 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the WCO output (wco_out) and SCB alternate functions listed in Table 2.
23 P0.6 bidirectional Port 0 GPIO bit 6 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the SRSS external clock and SCB alternate functions listed in Table 2.
24 XRES input External reset pin listed in Table 1 of the 32-pin QFN column; the provided text gives no electrical limits or polarity for it.
25 VCCD power_out Regulated digital supply output (1.8 V ± 5%) that must be bypassed to ground with an external 0.1 µF X5R ceramic or better capacitor and must not be connected to anything else in Mode 1.
26 VSSD power_in Ground pin for the digital section of the chip.
27 VDD power_in Power supply to all sections of the chip, specified at 1.8 V to 5.5 V in Mode 1 and 1.71 V to 1.89 V in Mode 2 where VDD and VCCD are shorted together.
28 VSSA power_in Ground pin for the analog section of the chip.
29 P1.0 bidirectional Port 1 GPIO bit 0 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the TCPWM, SCB UART and I2C/SPI alternate functions listed in Table 2.
30 P1.1 bidirectional Port 1 GPIO bit 1 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the TCPWM, SCB UART and I2C/SPI alternate functions listed in Table 2.
31 P1.2 bidirectional Port 1 GPIO bit 2 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the TCPWM, SCB and TCPWM trigger alternate functions listed in Table 2.
32 P1.3 bidirectional Port 1 GPIO bit 3 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the TCPWM, SCB and TCPWM trigger alternate functions listed in Table 2.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Infineon/Cypress Semicon
Package QFN-32(5x5)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDDD_ABS -0.5 6 V 21
Direct digital core voltage input relative to VSS VCCD_ABS -0.5 1.95 V 21
GPIO voltage VGPIO_ABS -0.5 V 21
Maximum current per GPIO IGPIO_ABS -25 25 mA 21
GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS IGPIO_injection -0.5 0.5 Current injected per pin 21
Electrostatic discharge human body model ESD_HBM 2200 V 21
Electrostatic discharge charged device model ESD_CDM 500 21
Pin current for latch-up LU -140 140 mA 21
Power supply input voltage VDD 1.8 5.5 V Internally regulated supply 22
Power supply input voltage (VCCD = VDD = VDDA) VDD 1.71 1.89 V Internally unregulated supply 22
Active mode current: execute from flash, CPU at 6 MHz IDD5 1.2 2 mA Active mode, VDD = 1.8 V to 5.5 V 22
Active mode current: execute from flash, CPU at 24 MHz IDD8 2.4 4 mA Active mode, VDD = 1.8 V to 5.5 V 22
Active mode current: execute from flash, CPU at 48 MHz IDD11 4.6 5.9 mA Active mode, VDD = 1.8 V to 5.5 V 22
I2C wakeup WDT, and comparators on IDD17 1.1 1.6 mA Sleep mode, VDDD = 1.8 V to 5.5 V (Regulator on); 6 MHz 22
I2C wakeup, WDT, and comparators on IDD20 1.4 1.9 mA Sleep mode, VDDD = 1.8 V to 5.5 V (Regulator on); 12 MHz 22
I2C wakeup, WDT, and Comparators on IDD23 0.7 0.9 mA Sleep mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed); 6 MHz 22
I2C wakeup, WDT, and Comparators on IDD23A 0.9 1.1 mA Sleep mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed); 12 MHz 22
I2C wakeup and WDT on IDD26 2.5 60 µA Deep Sleep mode, VDD = 1.8 V to 3.6 V (Regulator on) 22
Supply current while XRES asserted IDD_XR 2 5 mA 22
IMO operating current at 48 MHz IIMO1 250 µA 39
IMO operating current at 24 MHz IIMO2 180 µA 39
Frequency variation at 24, 32, and 48 MHz (trimmed) FIMOTOL1 -2 2 % At -40°C to 85°C, for industrial temperature range and original extended industrial range parts 39
IMO startup time TSTARTIMO 7 µs 39
ILO operating current IILO1 0.3 1.05 µA 40
ILO startup time TSTARTILO1 2 ms 40
ILO duty cycle TILODUTY 40 50 60 % 40
ILO frequency range FILOTRIM1 20 40 80 kHz 40
Frequency tolerance FTOL 50 250 ppm With 20-ppm crystal 40
Drive level PD 1 µW 40
Startup time TSTART 500 ms 40
Crystal load capacitance CL 6 12.5 pF 40
Operating current (high power mode) IWCO1 8 µA 40
Operating current (low power mode) IWCO2 1 µA 40
External clock input frequency ExtClkFreq 0 48 MHz 41
Duty cycle ExtClkDuty 45 55 % Measured at VDD/2 41
System clock source switching time TCLKSWITCH 3 4 Periods 41
Max delay added by Smart I/O in Bypass Mode PRG_BYPASS 1.6 ns 41
Operating ambient temperature TA -40 25 105 °C 44
Operating junction temperature TJ -40 125 °C 44
Maximum solder reflow peak temperature 260 °C Maximum time at peak temperature: 30 s 44
Package thermal resistance junction-to-ambient, 32 LEAD QFN TJA 20.8 °C/W 44
Package thermal resistance junction-to-case, 32 LEAD QFN TJC 5.9 °C/W 44

CAD (KiCad official)

  • Symbol: CY8C4024LQI-S402
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32(5x5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.55 mm tall, datasheet A, nominal). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
  • 3D model files: cy8c4024lqi-s402-etched.step / cy8c4024lqi-s402-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4024lqi-s402.step / cy8c4024lqi-s402.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon/Cypress Semicon datasheet (58 pp, sha256 493ab905a29a5d98, retrieved 2026-11-12, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF