component
CD40109BQNSRQ1
Public Made by Adomby adom
Texas Instruments Logic ICs, SO-16-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD40109BQNSRQ1
Texas Instruments · Logic ICs · SO-16-208mil
CD40109BQNSRQ1 from Texas Instruments, in a SO-16-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Low-voltage supply that sets logic 1 for the A, B, C, D inputs; it may exceed VDD and has no sequencing restriction. |
| 2 | ENABLE A | input | Three-state enable for output E; a low level puts E in high impedance. |
| 3 | A | input | Data input A with logic 1 = VCC and logic 0 = VSS, shifted to output E. |
| 4 | E | tri_state | Three-state level-shifted output for input A, with logic 1 = VDD and logic 0 = VSS. |
| 5 | F | tri_state | Three-state level-shifted output for input B, with logic 1 = VDD and logic 0 = VSS. |
| 6 | B | input | Data input B with logic 1 = VCC and logic 0 = VSS, shifted to output F. |
| 7 | ENABLE B | input | Three-state enable for output F; a low level puts F in high impedance. |
| 8 | VSS | power_in | Ground reference (logic 0) for the inputs and outputs; all voltages are referenced to this pin. |
| 9 | ENABLE C | input | Three-state enable for output G; a low level puts G in high impedance. |
| 10 | C | input | Data input C with logic 1 = VCC and logic 0 = VSS, shifted to output G. |
| 11 | G | tri_state | Three-state level-shifted output for input C, with logic 1 = VDD and logic 0 = VSS. |
| 12 | NC | unconnected | No internal connection. |
| 13 | H | tri_state | Three-state level-shifted output for input D, with logic 1 = VDD and logic 0 = VSS. |
| 14 | D | input | Data input D with logic 1 = VCC and logic 0 = VSS, shifted to output H. |
| 15 | ENABLE D | input | Three-state enable for output H; a low level puts H in high impedance. |
| 16 | VDD | power_in | High-voltage supply that sets logic 1 for the outputs; recommended range 3 V to 18 V, absolute maximum 20 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SO-16-208mil |
| Category | Logic ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply-voltage range (for TA = full package-temperature range) | VDD | 3 | 18 | V | for TA = full package-temperature range | 3 | |
| DC supply voltage range | VDD | -0.5 | 20 | V | Voltages referenced to VSS terminal | 3 | |
| Output voltage range, all outputs | -0.5 | V | All outputs; upper limit printed as VDD + 0.5 V | 3 | |||
| DC input current, any one input | -10 | 10 | mA | Any one input | 3 | ||
| Power dissipation per package | PD | 500 | mW | TA = -40°C to +100°C | 3 | ||
| Power dissipation per package at TA = +125°C | PD | 200 | mW | Derate linearly at TA = 100°C to +125°C, 12 mW/°C | 3 | ||
| Device dissipation per output transistor | 100 | mW | TA = full package-temperature range, all package types | 3 | |||
| Operating-temperature range | TA | -40 | 125 | °C | 3 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 3 | ||
| Latch-up performance | 50 | mA | per JESD 78, Class I | 3 | |||
| Max quiescent device current | IDD | 0.02 | 1 | µA | VIN = 0, 5 V; VDD = 5 V; TA = +25°C | 3 | |
| Max quiescent device current | IDD | 30 | µA | VIN = 0, 5 V; VDD = 5 V; TA = +125°C | 3 | ||
| Max quiescent device current | IDD | 0.02 | 2 | µA | VIN = 0, 10 V; VDD = 10 V; TA = +25°C | 3 | |
| Max quiescent device current | IDD | 60 | µA | VIN = 0, 10 V; VDD = 10 V; TA = +125°C | 3 | ||
| Max quiescent device current | IDD | 0.02 | 4 | µA | VIN = 0, 15 V; VDD = 15 V; TA = +25°C | 3 | |
| Max quiescent device current | IDD | 120 | µA | VIN = 0, 15 V; VDD = 15 V; TA = +125°C | 3 | ||
| Max quiescent device current | IDD | 0.04 | 20 | µA | VIN = 0, 20 V; VDD = 20 V; TA = +25°C | 3 | |
| Max quiescent device current | IDD | 600 | µA | VIN = 0, 20 V; VDD = 20 V; TA = +125°C | 3 | ||
| Min output low (sink) current | IOL | 0.51 | mA | VO = 0.4 V; VIN = 0, 5 V; VDD = 5 V; TA = +25°C | 3 | ||
| Min output low (sink) current | IOL | 0.36 | mA | VO = 0.4 V; VIN = 0, 5 V; VDD = 5 V; TA = +125°C | 3 | ||
| Min output low (sink) current | IOL | 1.3 | mA | VO = 0.5 V; VIN = 0, 10 V; VDD = 10 V; TA = +25°C | 3 | ||
| Min output low (sink) current | IOL | 0.9 | mA | VO = 0.5 V; VIN = 0, 10 V; VDD = 10 V; TA = +125°C | 3 | ||
| Min output low (sink) current | IOL | 3.4 | mA | VO = 1.5 V; VIN = 0, 15 V; VDD = 15 V; TA = +25°C | 3 | ||
| Min output low (sink) current | IOL | 2.4 | mA | VO = 1.5 V; VIN = 0, 15 V; VDD = 15 V; TA = +125°C | 3 | ||
| Min output high (source) current | IOH | -0.51 | mA | VO = 4.6 V; VIN = 0, 5 V; VDD = 5 V; TA = +25°C | 3 | ||
| Min output high (source) current | IOH | -0.36 | mA | VO = 4.6 V; VIN = 0, 5 V; VDD = 5 V; TA = +125°C | 3 | ||
| Min output high (source) current | IOH | -1.6 | mA | VO = 2.5 V; VIN = 0, 5 V; VDD = 5 V; TA = +25°C | 3 | ||
| Min output high (source) current | IOH | -1.15 | mA | VO = 2.5 V; VIN = 0, 5 V; VDD = 5 V; TA = +125°C | 3 | ||
| Min output high (source) current | IOH | -1.3 | mA | VO = 9.5 V; VIN = 0, 10 V; VDD = 10 V; TA = +25°C | 3 | ||
| Min output high (source) current | IOH | -0.9 | mA | VO = 9.5 V; VIN = 0, 10 V; VDD = 10 V; TA = +125°C | 3 | ||
| Min output high (source) current | IOH | -3.4 | mA | VO = 13.5 V; VIN = 0, 15 V; VDD = 15 V; TA = +25°C | 3 | ||
| Min output high (source) current | IOH | -2.4 | mA | VO = 13.5 V; VIN = 0, 15 V; VDD = 15 V; TA = +125°C | 3 | ||
| Max output voltage: low-level | VOL | 0 | 0.05 | V | VIN = 0, 5 V; VDD = 5 V | 3 | |
| Min output voltage: high-level | VOH | 4.95 | 5 | V | VIN = 0, 5 V; VDD = 5 V | 3 | |
| Min output voltage: high-level | VOH | 9.95 | 10 | V | VIN = 0, 10 V; VDD = 10 V | 3 | |
| Min output voltage: high-level | VOH | 14.95 | 15 | V | VIN = 0, 15 V; VDD = 15 V | 3 | |
| Max input current | IIN | -0.1 | 0.1 | µA | VIN = 0, 18 V; VDD = 18 V; TA = +25°C | 3 | |
| Max input current | IIN | -1 | 1 | µA | VIN = 0, 18 V; VDD = 18 V; TA = +125°C | 3 | |
| Max output leakage current (three-state) | IOUT | -0.4 | 0.4 | µA | VIN = 0, 18 V; VDD = 18 V; TA = +25°C | 3 | |
| Max output leakage current (three-state) | IOUT | -12 | 12 | µA | VIN = 0, 18 V; VDD = 18 V; TA = +125°C | 3 | |
| Max input low voltage | VIL | 1.5 | V | VDD = 5 V | 3 | ||
| Max input low voltage | VIL | 3 | V | VDD = 10 V | 3 | ||
| Min input high voltage | VIH | 3.5 | V | VDD = 5 V | 3 | ||
| Min input high voltage | VIH | 7 | V | VDD = 10 V | 3 | ||
| Propagation delay time, high-to-low level, data input to output | tPHL | 300 | 600 | ns | VCC = 5 V, VDD = 10 V, L-H; TA = 25°C, tr/tf = 20 ns, CL = 50 pF, RL = 200 kΩ | 4 | |
| Propagation delay time, high-to-low level, data input to output | tPHL | 220 | 440 | ns | VCC = 5 V, VDD = 15 V, L-H; TA = 25°C, tr/tf = 20 ns, CL = 50 pF, RL = 200 kΩ | 4 | |
| Propagation delay time, low-to-high level, data input to output | tPLH | 130 | 260 | ns | VCC = 5 V, VDD = 10 V, L-H; TA = 25°C, tr/tf = 20 ns, CL = 50 pF, RL = 200 kΩ | 4 | |
| Propagation delay time, low-to-high level, data input to output | tPLH | 120 | 240 | ns | VCC = 5 V, VDD = 15 V, L-H; TA = 25°C, tr/tf = 20 ns, CL = 50 pF, RL = 200 kΩ | 4 | |
| Propagation delay time, 3-state disable, output high to high impedance | tPHZ | 60 | 120 | ns | VCC = 5 V, VDD = 10 V, L-H; TA = 25°C, tr/tf = 20 ns, CL = 50 pF, RL = 1 kΩ | 4 | |
| Propagation delay time, 3-state disable, output high to high impedance | tPHZ | 75 | 150 | ns | VCC = 5 V, VDD = 15 V, L-H; TA = 25°C, tr/tf = 20 ns, CL = 50 pF, RL = 1 kΩ | 4 | |
| Propagation delay time, 3-state disable, output low to high impedance | tPLZ | 370 | 740 | ns | VCC = 5 V, VDD = 10 V, L-H; TA = 25°C, tr/tf = 20 ns, CL = 50 pF, RL = 1 kΩ | 4 | |
| Propagation delay time, 3-state disable, output low to high impedance | tPLZ | 300 | 600 | ns | VCC = 5 V, VDD = 15 V, L-H; TA = 25°C, tr/tf = 20 ns, CL = 50 pF, RL = 1 kΩ | 4 | |
| Propagation delay time, 3-state enable, output high impedance to high | tPZH | 320 | 640 | ns | VCC = 5 V, VDD = 10 V, L-H; TA = 25°C, tr/tf = 20 ns, CL = 50 pF, RL = 1 kΩ | 4 | |
| Propagation delay time, 3-state enable, output high impedance to high | tPZH | 230 | 460 | ns | VCC = 5 V, VDD = 15 V, L-H; TA = 25°C, tr/tf = 20 ns, CL = 50 pF, RL = 1 kΩ | 4 | |
| Transition time | tTHL, tTLH | 50 | 100 | ns | VCC = 5 V, VDD = 10 V, L-H; TA = 25°C, tr/tf = 20 ns, CL = 50 pF, RL = 200 kΩ | 4 | |
| Transition time | tTHL, tTLH | 40 | 80 | ns | VCC = 5 V, VDD = 15 V, L-H; TA = 25°C, tr/tf = 20 ns, CL = 50 pF, RL = 200 kΩ | 4 | |
| Input capacitance | Ci | 5 | 7.5 | pF | Any input | 4 |
CAD (KiCad official)
- Symbol:
CD40109BQNSRQ1 - Footprint:
Package_SO:SO-16_5.3x10.2mm_P1.27mm - 3D model: SO-16-208mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.75 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
cd40109bqnsrq1-etched.step/cd40109bqnsrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd40109bqnsrq1.step/cd40109bqnsrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (16 pp, sha256
011f47dc8b314b58, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).