component
LM37102CGDP
Public Made by Adomby adom
HTC Korea TAEJIN Tech Linear Voltage Regulators (LDO), SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM37102CGDP
HTC Korea TAEJIN Tech · Linear Voltage Regulators (LDO) · SOP-8-EP
LM37102CGDP from HTC Korea TAEJIN Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Active-high chip enable with TTL/CMOS compatible thresholds (logic low ≤0.25V off, logic high ≥2.0V on), may be tied to VIN, operating rating up to 16V. |
| 2 | VIN | power_in | Input supply, operating range 2.5V to 16V (absolute maximum 20V). |
| 3 | VOUT | power_out | Regulated output delivering up to 1A, with a minimum recommended output capacitor of 2.2uF. |
| 4 | FLG/ADJ | input | Error flag output or output adjust; on this adjustable device it connects to the R1/R2 divider that sets VOUT with a 1.24V reference. |
| 5 | GND | power_in | Ground. |
| 6 | GND | power_in | Ground. |
| 7 | GND | power_in | Ground. |
| 8 | GND | power_in | Ground. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HTC Korea TAEJIN Tech |
| Package | SOP-8-EP |
| Category | Power Management ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VIN | -0.3 | 20 | V | 1 | ||
| Enable Voltage | VEN | 20 | V | 1 | |||
| Lead Temperature | TSOL | 260 | ℃ | Soldering, 5 sec | 1 | ||
| Storage Temperature Range | TSTG | -65 | 150 | ℃ | 1 | ||
| Supply Voltage | VIN | 2.5 | 16 | V | 2 | ||
| Enable Voltage | VEN | 16 | V | 2 | |||
| Junction Temperature | TJ | -40 | 125 | ℃ | 2 | ||
| Output Voltage accuracy | VOUT | -1 | 1 | % | 10mA | 4 | |
| Output Voltage accuracy | VOUT | -2 | 2 | % | 10mA ≤ IOUT ≤ 1A, VOUT+1V ≤ VIN ≤16V | 4 | |
| Adjustable Pin Voltage | VADJ | 1.228 | 1.24 | 1.252 | V | 4 | |
| Adjustable Pin Voltage | VADJ | 1.215 | 1.265 | V | 4 | ||
| Adjustable Pin Voltage | VADJ | 1.203 | 1.277 | V | Note 8 | 4 | |
| Adjust Pin Bias Current | IADJ | 3 | 20 | uA | 4 | ||
| Line Regulation | 0.06 | 0.5 | % | IOUT=1mA, VOUT +1V ≤ VIN ≤ 16V | 4 | ||
| Load Regulation | 0.2 | 1 | % | VIN= VOUT +1V, 1mA ≤ IOUT ≤ 1A | 4 | ||
| Dropout Voltage | VDO | 100 | 250 | mV | IOUT=100mA, ΔVOUT = -1% | 4 | |
| Dropout Voltage | VDO | 500 | 630 | mV | IOUT=1A, ΔVOUT = -1% | 4 | |
| Current Limit | IOUT(lim) | 1.4 | 2.5 | A | VOUT=0V, VIN=VOUT+1V | 4 | |
| Enable Input Voltage logic low (off) | VEN | 0.25 | V | logic low (off) | 4 | ||
| Enable Input Voltage logic high (on) | VEN | 2 | V | logic high (on) | 4 | ||
| Enable Input Current | IEN | 3 | 30 | μA | VEN=16V | 4 | |
| Enable Input Current | IEN | 0.01 | 1 | μA | VEN=0.0V | 4 | |
| Ground Current | IGND | 3.8 | mA | IOUT=100mA, VIN= VOUT+1V | 4 | ||
| Ground Current | IGND | 25 | mA | IOUT=1A, VIN= VOUT+1V | 4 | ||
| Output Voltage Temp. Coefficient | ΔVOUT/ΔT | 100 | ppm/ °C | Note 4 | 4 | ||
| Delay time to Nominal Output Voltage | TEN | 50 | μs | IOUT =10mA, VIN =VOUT +1V, VEN =0V to VIN | 4 | ||
| Delay time to Nominal Output Voltage | TEN | 250 | μs | IOUT =500mA, VIN =VOUT +1V, VEN =0V to VIN | 4 | ||
| Delay time to Nominal Output Voltage | TEN | 350 | μs | IOUT =1.0A, VIN =VOUT +1V, VEN =0V to VIN | 4 | ||
| Thermal Resistance Junction-To-Ambient SOP-8PP | θJA-SOT-8PP | 75 | °C/W | No heat sink / No air flow / No adjacent heat source / 20 mm2 copper area. (TA=25°C) | 7 |
CAD (KiCad official)
- Symbol:
LM37102CGDP - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
lm37102cgdp-etched.step/lm37102cgdp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm37102cgdp.step/lm37102cgdp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HTC Korea TAEJIN Tech datasheet (8 pp, sha256
3af1b1dfbbec7037, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).