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9DBL411BGLFT

Public Made by Adom

by adom

RENESAS Clock Buffers, Drivers, Distributors, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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9DBL411BGLFT

RENESAS · Clock Buffers, Drivers, Distributors · TSSOP-20

9DBL411BGLFT from RENESAS, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE0# input Output Enable control for DIF0 differential output pair; 0 = enabled, 1 = tristate (Low-Low).
2 DIF_INC input Complement side of differential input clock.
3 DIF_INT input True side of differential input clock.
4 VDDA power_in 3.3V analog core supply voltage.
5 GNDA power_in Ground for analog core.
6 OE3# input Output Enable control for DIF3 differential output pair; 0 = enabled, 1 = tristate (Low-Low).
7 DIF3C_LPR output Complement clock of low power differential output pair DIF3 (no 50 ohm shunt resistor to ground required).
8 DIF3T_LPR output True clock of low power differential output pair DIF3 (no 50 ohm shunt resistor to ground required).
9 VDD_IO power_in Power supply for low power differential outputs, 1.05V to 3.3V nominal.
10 GND power_in Ground pin.
11 DIF2C_LPR output Complement clock of low power differential output pair DIF2 (no 50 ohm shunt resistor to ground required).
12 DIF2T_LPR output True clock of low power differential output pair DIF2 (no 50 ohm shunt resistor to ground required).
13 OE2# input Output Enable control for DIF2 differential output pair; 0 = enabled, 1 = tristate (Low-Low).
14 DIF1C_LPR output Complement clock of low power differential output pair DIF1 (no 50 ohm shunt resistor to ground required).
15 DIF1T_LPR output True clock of low power differential output pair DIF1 (no 50 ohm shunt resistor to ground required).
16 OE1# input Output Enable control for DIF1 differential output pair; 0 = enabled, 1 = tristate (Low-Low).
17 GND power_in Ground pin.
18 VDD_IO power_in Power supply for low power differential outputs, 1.05V to 3.3V nominal.
19 DIF0C_LPR output Complement clock of low power differential output pair DIF0 (no 50 ohm shunt resistor to ground required).
20 DIF0T_LPR output True clock of low power differential output pair DIF0 (no 50 ohm shunt resistor to ground required).

Key specifications

Parameter Value
Manufacturer RENESAS
Package TSSOP-20
Category Clock/Timing
Pins 20

CAD (KiCad official)

  • Symbol: 9DBL411BGLFT
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 9dbl411bglft-etched.step / 9dbl411bglft-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 9dbl411bglft.step / 9dbl411bglft.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (10 pp, sha256 70fa6701e0fc6ed5, retrieved 2026-09-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF