SN74HC10QPWREP from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1A	input	Input A of NAND gate 1; unused inputs must be held at VCC or GND to ensure proper device operation.
2	1B	input	Input B of NAND gate 1; unused inputs must be held at VCC or GND to ensure proper device operation.
3	2A	input	Input A of NAND gate 2; unused inputs must be held at VCC or GND to ensure proper device operation.
4	2B	input	Input B of NAND gate 2; unused inputs must be held at VCC or GND to ensure proper device operation.
5	2C	input	Input C of NAND gate 2; unused inputs must be held at VCC or GND to ensure proper device operation.
6	2Y	output	Output Y of NAND gate 2; outputs can drive up to 10 LSTTL loads and provide ±4-mA output drive at 5 V.
7	GND	power_in	Ground reference for the device.
8	3Y	output	Output Y of NAND gate 3; outputs can drive up to 10 LSTTL loads and provide ±4-mA output drive at 5 V.
9	3A	input	Input A of NAND gate 3; unused inputs must be held at VCC or GND to ensure proper device operation.
10	3B	input	Input B of NAND gate 3; unused inputs must be held at VCC or GND to ensure proper device operation.
11	3C	input	Input C of NAND gate 3; unused inputs must be held at VCC or GND to ensure proper device operation.
12	1Y	output	Output Y of NAND gate 1; outputs can drive up to 10 LSTTL loads and provide ±4-mA output drive at 5 V.
13	1C	input	Input C of NAND gate 1; unused inputs must be held at VCC or GND to ensure proper device operation.
14	VCC	power_in	Supply voltage, specified from 2 V to 6 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-14
Category	Logic
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	2	5	6	V		2
High-level input voltage	VIH	1.5			V	VCC = 2 V	2
High-level input voltage	VIH	3.15			V	VCC = 4.5 V	2
High-level input voltage	VIH	4.2			V	VCC = 6 V	2
Low-level input voltage	VIL			0.5	V	VCC = 2 V	2
Low-level input voltage	VIL			1.35	V	VCC = 4.5 V	2
Low-level input voltage	VIL			1.8	V	VCC = 6 V	2
Input voltage	VI	0			V		2
Output voltage	VO	0			V		2
Input transition rise/fall time	∆t/∆v			1000	ns	VCC = 2 V	2
Input transition rise/fall time	∆t/∆v			500	ns	VCC = 4.5 V	2
Input transition rise/fall time	∆t/∆v			400	ns	VCC = 6 V	2
Operating free-air temperature	TA	-40		125	°C		2
Supply voltage range	VCC	-0.5		7	V		2
Input clamp current	IIK	-20		20	mA	VI < 0 or VI > VCC	2
Output clamp current	IOK	-20		20	mA	VO < 0 or VO > VCC	2
Continuous output current	IO	-25		25	mA	VO = 0 to VCC	2
Continuous current through VCC or GND		-50		50	mA		2
Storage temperature range	Tstg	-65		150	°C		2
Package thermal impedance PW package	θJA		113		°C/W	PW package	2
High-level output voltage	VOH	1.9	1.998		V	IOH = −20 µA, VI = VIH or VIL, VCC 2 V	3
High-level output voltage	VOH	4.4	4.499		V	IOH = −20 µA, VI = VIH or VIL, VCC 4.5 V	3
High-level output voltage	VOH	5.9	5.999		V	IOH = −20 µA, VI = VIH or VIL, VCC 6 V	3
High-level output voltage	VOH	3.7	4.3		V	IOH = −4 mA, VI = VIH or VIL, VCC 4.5 V	3
High-level output voltage	VOH	5.2	5.8		V	IOH = −5.2 mA, VI = VIH or VIL, VCC 6 V	3
Low-level output voltage	VOL		0.002	0.1	V	IOL = 20 µA, VI = VIH or VIL, VCC 2 V	3
Low-level output voltage	VOL		0.001	0.1	V	IOL = 20 µA, VI = VIH or VIL, VCC 4.5 V	3
Low-level output voltage	VOL		0.17	0.4	V	IOL = 4 mA, VI = VIH or VIL, VCC 4.5 V	3
Low-level output voltage	VOL		0.15	0.4	V	IOL = 5.2 mA, VI = VIH or VIL, VCC 6 V	3
Input current	II	-1000	0.1	1000	nA	VI = VCC or 0, VCC 6 V	3
Supply current	ICC		2	40	µA	VI = VCC or 0, IO = 0, VCC 6 V	3
Input capacitance	Ci		3	10	pF	2 V to 6 V	3
Propagation delay tpd A, B, or C to Y	tpd		35	145	ns	CL = 50 pF, VCC 2 V	3
Propagation delay tpd A, B, or C to Y	tpd		10	29	ns	CL = 50 pF, VCC 4.5 V	3
Propagation delay tpd A, B, or C to Y	tpd		9	25	ns	CL = 50 pF, VCC 6 V	3
Output transition time tt Y	tt		23	110	ns	CL = 50 pF, VCC 2 V	3
Output transition time tt Y	tt		6	22	ns	CL = 50 pF, VCC 4.5 V	3
Output transition time tt Y	tt		5	19	ns	CL = 50 pF, VCC 6 V	3
Power dissipation capacitance per gate	Cpd		25		pF	No load	3

CAD (KiCad official)

Symbol: SN74HC10QPWREP
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: sn74hc10qpwrep-etched.step / sn74hc10qpwrep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc10qpwrep.step / sn74hc10qpwrep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (15 pp, sha256 5581eb0951d7af68, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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SN74HC10QPWREP

Verified SN74HC10QPWREP

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3D Model

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