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C8051F021-GQR

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SKYWORKS SILICON LABS Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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C8051F021-GQR

SKYWORKS SILICON LABS · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)

C8051F021-GQR from SKYWORKS SILICON LABS, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CP1- input Comparator 1 Inverting Input.
2 CP1+ input Comparator 1 Non-Inverting Input.
3 CP0- input Comparator 0 Inverting Input.
4 CP0+ input Comparator 0 Non-Inverting Input.
5 AGND power_in Analog Ground. Must be tied to Ground.
6 AV+ power_in Analog Supply Voltage. Must be tied to +2.7 to +3.6 V.
7 VREF power_in Bandgap Voltage Reference Output (all devices); on C8051F021/3 this pin is also the DAC Voltage Reference Input.
8 VREFA input ADC0 and ADC1 Voltage Reference Input.
9 AIN0.0 input ADC0 Input Channel 0 (see ADC0 Specification for complete description).
10 AIN0.1 input ADC0 Input Channel 1 (see ADC0 Specification for complete description).
11 AIN0.2 input ADC0 Input Channel 2 (see ADC0 Specification for complete description).
12 AIN0.3 input ADC0 Input Channel 3 (see ADC0 Specification for complete description).
13 AIN0.4 input ADC0 Input Channel 4 (see ADC0 Specification for complete description).
14 AIN0.5 input ADC0 Input Channel 5 (see ADC0 Specification for complete description).
15 AIN0.6 input ADC0 Input Channel 6 (see ADC0 Specification for complete description).
16 AIN0.7 input ADC0 Input Channel 7 (see ADC0 Specification for complete description).
17 XTAL1 input Crystal Input, the return for the internal oscillator; if overdriven by an external CMOS clock this pin becomes the system clock.
18 XTAL2 output Crystal Output, the excitation driver for a crystal or ceramic resonator.
19 MONEN input VDD Monitor Enable; when tied high the internal VDD monitor forces a system reset when VDD is below 2.7 V, and when tied low the monitor is disabled.
20 AIN1.7/A15/P1.7 bidirectional ADC1 analog input channel 7 (AIN1.7) or External Memory Interface address bit 15 (non-multiplexed mode) or Port 1.7 GPIO, selected by P1MDIN and the Crossbar.
21 AIN1.6/A14/P1.6 bidirectional ADC1 analog input channel 6 (AIN1.6) or External Memory Interface address bit 14 (non-multiplexed mode) or Port 1.6 GPIO.
22 AIN1.5/A13/P1.5 bidirectional ADC1 analog input channel 5 (AIN1.5) or External Memory Interface address bit 13 (non-multiplexed mode) or Port 1.5 GPIO.
23 AIN1.4/A12/P1.4 bidirectional ADC1 analog input channel 4 (AIN1.4) or External Memory Interface address bit 12 (non-multiplexed mode) or Port 1.4 GPIO.
24 VDD power_in Digital Supply Voltage. Must be tied to +2.7 to +3.6 V.
25 DGND power_in Digital Ground. Must be tied to Ground.
26 AIN1.3/A11/P1.3 bidirectional ADC1 analog input channel 3 (AIN1.3) or External Memory Interface address bit 11 (non-multiplexed mode) or Port 1.3 GPIO.
27 AIN1.2/A10/P1.2 bidirectional ADC1 analog input channel 2 (AIN1.2) or External Memory Interface address bit 10 (non-multiplexed mode) or Port 1.2 GPIO.
28 AIN1.1/A9/P1.1 bidirectional ADC1 analog input channel 1 (AIN1.1) or External Memory Interface address bit 9 (non-multiplexed mode) or Port 1.1 GPIO.
29 AIN1.0/A8/P1.0 bidirectional ADC1 analog input channel 0 (AIN1.0) or External Memory Interface address bit 8 (non-multiplexed mode) or Port 1.0 GPIO.
30 A15m/A7/P2.7 bidirectional Port 2.7 GPIO, or External Memory Interface address bit 15 (multiplexed mode) or address bit 7 (non-multiplexed mode).
31 A14m/A6/P2.6 bidirectional Port 2.6 GPIO, or External Memory Interface address bit 14 (multiplexed mode) or address bit 6 (non-multiplexed mode).
32 A13m/A5/P2.5 bidirectional Port 2.5 GPIO, or External Memory Interface address bit 13 (multiplexed mode) or address bit 5 (non-multiplexed mode).
33 A12m/A4/P2.4 bidirectional Port 2.4 GPIO, or External Memory Interface address bit 12 (multiplexed mode) or address bit 4 (non-multiplexed mode).
34 A11m/A3/P2.3 bidirectional Port 2.3 GPIO, or External Memory Interface address bit 11 (multiplexed mode) or address bit 3 (non-multiplexed mode).
35 A10m/A2/P2.2 bidirectional Port 2.2 GPIO, or External Memory Interface address bit 10 (multiplexed mode) or address bit 2 (non-multiplexed mode).
36 A9m/A1/P2.1 bidirectional Port 2.1 GPIO, or External Memory Interface address bit 9 (multiplexed mode) or address bit 1 (non-multiplexed mode).
37 A8m/A0/P2.0 bidirectional Port 2.0 GPIO, or External Memory Interface address bit 8 (multiplexed mode) or address bit 0 (non-multiplexed mode).
38 AD7/D7/P3.7/IE7 bidirectional Port 3.7 GPIO, External Memory Address/Data bit 7 (multiplexed) or data bit 7 (non-multiplexed), and edge-sensitive external interrupt IE7 input.
39 AD6/D6/P3.6/IE6 bidirectional Port 3.6 GPIO, External Memory Address/Data bit 6 (multiplexed) or data bit 6 (non-multiplexed), and edge-sensitive external interrupt IE6 input.
40 DGND power_in Digital Ground. Must be tied to Ground.
41 VDD power_in Digital Supply Voltage. Must be tied to +2.7 to +3.6 V.
42 AD5/D5/P3.5 bidirectional Port 3.5 GPIO, or External Memory Address/Data bit 5 (multiplexed) or data bit 5 (non-multiplexed).
43 AD4/D4/P3.4 bidirectional Port 3.4 GPIO, or External Memory Address/Data bit 4 (multiplexed) or data bit 4 (non-multiplexed).
44 AD3/D3/P3.3 bidirectional Port 3.3 GPIO, or External Memory Address/Data bit 3 (multiplexed) or data bit 3 (non-multiplexed).
45 AD2/D2/P3.2 bidirectional Port 3.2 GPIO, or External Memory Address/Data bit 2 (multiplexed) or data bit 2 (non-multiplexed).
46 AD1/D1/P3.1 bidirectional Port 3.1 GPIO, or External Memory Address/Data bit 1 (multiplexed) or data bit 1 (non-multiplexed).
47 AD0/D0/P3.0 bidirectional Port 3.0 GPIO, or External Memory Address/Data bit 0 (multiplexed) or data bit 0 (non-multiplexed).
48 /WR/P0.7 bidirectional External Memory Interface write strobe /WR, or Port 0.7 GPIO; when EMIFLE is set the Crossbar skips this pin.
49 /RD/P0.6 bidirectional External Memory Interface read strobe /RD, or Port 0.6 GPIO; when EMIFLE is set the Crossbar skips this pin.
50 ALE/P0.5 bidirectional ALE strobe for the External Memory Address bus (multiplexed mode), or Port 0.5 GPIO.
51 P0.4 bidirectional Port 0.4 GPIO; the output mode is set by P0MDOUT and the pin may be assigned by the Crossbar.
52 P0.3 bidirectional Port 0.3 GPIO; the output mode is set by P0MDOUT and the pin may be assigned by the Crossbar.
53 P0.2 bidirectional Port 0.2 GPIO; the output mode is set by P0MDOUT and the pin may be assigned by the Crossbar.
54 P0.1 bidirectional Port 0.1 GPIO; the output mode is set by P0MDOUT and the pin may be assigned by the Crossbar.
55 P0.0 bidirectional Port 0.0 GPIO; the output mode is set by P0MDOUT and the pin may be assigned by the Crossbar.
56 DGND power_in Digital Ground. Must be tied to Ground.
57 VDD power_in Digital Supply Voltage. Must be tied to +2.7 to +3.6 V.
58 TMS input JTAG Test Mode Select with internal pull-up.
59 TCK input JTAG Test Clock with internal pull-up.
60 TDI input JTAG Test Data Input with internal pull-up; TDI is latched on the rising edge of TCK.
61 TDO tri_state JTAG Test Data Output with internal pull-up; data is shifted out on the falling edge of TCK and TDO is a tri-state driver.
62 /RST bidirectional Device Reset; open-drain output of the internal VDD monitor, driven low when VDD is below 2.7 V and MONEN is high, and an external source can drive it low to reset the system.
63 DAC1 output Digital to Analog Converter 1 voltage output (see DAC Specification for complete description).
64 DAC0 output Digital to Analog Converter 0 voltage output (see DAC Specification for complete description).

Key specifications

Parameter Value
Manufacturer SKYWORKS SILICON LABS
Package TQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -55 125 °C 31
Storage Temperature -65 150 °C 31
Voltage on any Pin (except VDD and Port I/O) with respect to DGND -0.3 V 31
Voltage on any Port I/O Pin or /RST with respect to DGND -0.3 5.8 V 31
Voltage on VDD with respect to DGND -0.3 4.2 V 31
Maximum Total current through VDD, AV+, DGND, and AGND 800 mA 31
Maximum output current sunk by any Port pin 100 mA 31
Maximum output current sunk by any other I/O pin 50 mA 31
Maximum output current sourced by any Port pin 100 mA 31
Maximum output current sourced by any other I/O pin 50 mA 31
Analog Supply Voltage 2.7 3 3.6 V 32
Analog Supply Current 1.7 mA AV+=2.7 V, Internal REF, ADC, DAC, Comparators all active 32
Analog Supply Current with analog sub-systems inactive 0.2 µA AV+=2.7 V, Internal REF, ADC, DAC, Comparators all disabled, oscillator disabled, VDD Monitor disabled 32
Digital Supply Voltage 2.7 3 3.6 V 32
Digital Supply Current with CPU active 10 mA VDD=2.7 V, Clock=25 MHz 32
Digital Supply Current with CPU active 0.5 mA VDD=2.7 V, Clock=1 MHz 32
Digital Supply Current with CPU active 20 µA VDD=2.7 V, Clock=32 kHz 32
Digital Supply Current with CPU inactive (not accessing FLASH) 5 mA VDD=2.7 V, Clock=25 MHz 32
Digital Supply Current with CPU inactive (not accessing FLASH) 0.2 mA VDD=2.7 V, Clock=1 MHz 32
Digital Supply Current with CPU inactive (not accessing FLASH) 10 µA VDD=2.7 V, Clock=32 kHz 32
Digital Supply Current (shutdown) 0.2 µA VDD=2.7 V, Oscillator not running, VDD Monitor disabled 32
Digital Supply RAM Data Retention Voltage 1.5 V 32
Specified Operating Temperature Range -40 85 °C 32
SYSCLK (system clock frequency) SYSCLK 0 25 MHz 32
Integral Nonlinearity -1 1 LSB 82
Differential Nonlinearity -1 1 LSB Guaranteed Monotonic 82
Offset Error -0.3 0.5 0.3 LSB 82
Full Scale Error -0.2 -1 0.2 LSB Differential mode 82
Total Harmonic Distortion -51 dB Up to the 5th harmonic 82
Input Voltage Range 0 V 82
Power Supply Current (AV+ supplied to ADC1) 420 900 µA Operating Mode, 500 ksps 82
Power Supply Rejection -0.3 0.3 mV/V 82
Integral Nonlinearity -2 2 LSB 89
Differential Nonlinearity -1 1 LSB 89
Output Noise 250 µVrms No Output Filter 89
Offset Error -30 3 30 mV Data Word = 0x014 89
Gain Error -60 20 60 mV 89
VDD Power Supply Rejection Ratio -60 dB 89
Output Impedance in Shutdown Mode 100 k DACnEN = 0 89
Output Short-Circuit Current 15 mA Data Word = 0xFFF 89
Voltage Output Slew Rate 0.44 V/µs Load = 40pF 89
Output Settling Time to 1/2 LSB 10 µs Load = 40pF, Output swing from code 0xFFF to 0x014 89
Startup Time 10 µs 89
Load Regulation 60 ppm IL = 0.01mA to 0.3mA at code 0xFFF 89
Power Supply Current (AV+ supplied to DAC) 110 400 µA Data Word = 0x7FF 89
Output Voltage 2.36 2.43 2.48 V 25°C ambient 94
VREF Short-Circuit Current 30 mA 94
VREF Turn-on Time 1 2 ms 4.7µF tantalum, 0.1µF ceramic bypass 94
VREF Turn-on Time 2 20 µs 0.1µF ceramic bypass 94
VREF Turn-on Time 3 10 µs no bypass cap 94
External Reference Input Voltage Range 1 V EXTERNAL REFERENCE (REFBE = 0) 94
Output Low Voltage (VOL) 0.1 V IOL = 10 µA 161
Output Low Voltage (VOL) 0.6 V IOL = 8.5 mA 161
Output Low Voltage (VOL) 1 V IOL = 25 mA 161
/RST Output Low Voltage 0.6 V IOL = 8.5 mA, VDD = 2.7 V to 3.6 V 133
VDD POR Threshold (VRST) VRST 2.4 2.55 2.7 V 133
Reset Time Delay 80 100 120 ms /RST rising edge after VDD crosses VRST threshold 133
Missing Clock Detector Timeout 100 220 500 µs from last system clock to reset initiation 133
Internal Oscillator Frequency 1.5 2 2.4 MHz OSCICN.[1:0] = 00 136
Internal Oscillator Frequency 3.1 4 4.8 MHz OSCICN.[1:0] = 01 136
Internal Oscillator Frequency 6.2 8 9.6 MHz OSCICN.[1:0] = 10 136
Internal Oscillator Frequency 12.3 16 19.2 MHz OSCICN.[1:0] = 11 136

CAD (KiCad official)

  • Symbol: C8051F021-GQR
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: c8051f021-gqr-etched.step / c8051f021-gqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f021-gqr.step / c8051f021-gqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SKYWORKS SILICON LABS datasheet (272 pp, sha256 805cf92c6d5b39ca, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF