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TPS54672PWPR

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Texas Instruments DC-DC Converters, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TPS54672PWPR

Texas Instruments · DC-DC Converters · HTSSOP-28-EP

TPS54672PWPR from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground and return for the compensation network/output divider, VBIAS capacitor, and RT resistor; connect the PowerPAD to AGND.
2 VSENSE input Error amplifier inverting input, connected to the output voltage through the compensation network/output divider.
3 COMP output Error amplifier output; the frequency compensation network connects from COMP to VSENSE.
4 STATUS output Open-drain output that is asserted low when VIN is below the UVLO threshold, VBIAS and the internal reference are not settled, or thermal shutdown is active, and is otherwise high; sink current is limited to 10 mA absolute maximum.
5 BOOT output Bootstrap output; a 0.022 µF to 0.1 µF low-ESR capacitor from BOOT to PH generates the floating drive for the high-side FET driver, with an absolute maximum of 17 V.
6 PH output Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V.
7 PH output Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V.
8 PH output Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V.
9 PH output Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V.
10 PH output Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V.
11 PH output Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V.
12 PH output Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V.
13 PH output Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V.
14 PH output Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum voltage is −0.3 V to 10 V.
15 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended.
16 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended.
17 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended.
18 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended.
19 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended.
20 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package.
21 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package.
22 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package.
23 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package.
24 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating over 3.0 V to 6.0 V and bypassed to PGND with a low-ESR 10 µF ceramic capacitor placed close to the package.
25 VBIAS power_out Internal bias regulator output supplying internal circuitry, nominally 2.70 V to 2.90 V with up to 100 µA static resistive load, bypassed to AGND with a 0.1 µF to 1.0 µF low-ESR ceramic capacitor.
26 REFIN input External reference input, a high-impedance input to the slow-start and error amplifier circuits with an input range of 0 V to 1.8 V.
27 ENA input Enable input; a logic high (1.40 V or greater) enables the oscillator, PWM control and MOSFET drivers, and a logic low (0.82 V or less) disables operation into a low quiescent current state, with an absolute maximum of 7 V.
28 RT input Frequency-setting resistor input; connect a 68 kΩ to 180 kΩ resistor to AGND to set the switching frequency from 280 kHz to 700 kHz, or leave it floating for the internal 350 kHz default.
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-28-EP
Category Power Supply Chip
Pins 29

CAD (KiCad official)

  • Symbol: TPS54672PWPR
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
  • 3D model files: tps54672pwpr-etched.step / tps54672pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54672pwpr.step / tps54672pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 9158e2ffacac2f01, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF