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HC32F030F8UA-QN32TR

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XHSC Microcontrollers (MCU/MPU/SOC), QFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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Datasheet

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Contents

README

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HC32F030F8UA-QN32TR

XHSC · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(5x5)

HC32F030F8UA-QN32TR from XHSC, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCAP passive Internal 1.5V LDO regulator decoupling pin. Requires an external ~1uF ceramic capacitor to DVSS. Do not drive externally.
2 PD00/XTHI/I2C0_SDA/UART1_TXD bidirectional General purpose I/O PD00. Alt functions: XTHI (external high-speed crystal input 4-32MHz), I2C0_SDA, UART1_TXD.
3 PD01/XTHO/I2C0_SCL/TIM4_CHB/UART1_RXD bidirectional General purpose I/O PD01. Alt functions: XTHO (external high-speed crystal output), I2C0_SCL, TIM4_CHB, UART1_RXD.
4 RESETB input Active-low external reset input with internal pull-up. Pull low > tRSTB to reset the MCU.
5 AVCC power_in Analog supply for ADC, comparators, op-amps and reference (1.8-5.5V). Should be connected to DVCC and decoupled to AVSS/DVSS with 100nF + bulk cap.
6 PA00 bidirectional GPIO PA00 with rich alternate functions: UART1_CTS, TIM0_ETR, VC0_OUT, TIM1_CHA, TIM3_ETR, TIM0_CHA; analog: AIN0, VC0_INP4, VC0_INN0, VC1_INP0, VC1_INN4.
7 PA01 bidirectional GPIO PA01. Alt functions: UART1_RTS, TIM0_CHB, TIM1_ETR, TIM1_CHB, HCLK_OUT, SPI1_MOSI, UART1_TXD, TIM0_CHA; analog: AIN1, VC0_INP5, VC0_INN1, VC1_INP1, VC1_INN5.
8 PA02 bidirectional GPIO PA02. Alt functions: VC1_OUT, TIM1_CHA, TIM2_CHA, PCLK_OUT, SPI1_MISO; analog: AIN2, VC0_INP6, VC0_INN2, VC1_INP2.
9 PA03 bidirectional GPIO PA03. Alt functions: UART1_RXD, TIM0_GATE, TIM1_CHB, TIM2_CHB, SPI1_CS, TIM3_CH1A, TIM5_CHA; analog: AIN3, VC0_INP7, VC0_INN3, VC1_INP3.
10 PA04 bidirectional GPIO PA04. Alt functions: SPI0_CS, UART1_TXD, PCA_CH4, TIM2_ETR, TIM5_CHA, LVD_OUT, TIM3_CH2B; analog: AIN4, VC0_INP8, VC0_INN4, VC1_INP4.
11 PA05 bidirectional GPIO PA05. Alt functions: SPI0_CLK, TIM0_ETR, PCA_ECI, TIM0_CHA, TIM5_CHB, XTL_OUT, XTH_OUT; analog: AIN5, VC0_INP9, VC0_INN5, VC1_INP5.
12 PA06 bidirectional GPIO PA06. Alt functions: SPI0_MISO, PCA_CH0, TIM3_BK, TIM1_CHA, VC0_OUT, TIM3_GATE; analog: AIN6, VC0_INP10, VC0_INN6.
13 PA07 bidirectional GPIO PA07. Alt functions: SPI0_MOSI, PCA_CH1, HCLK_OUT, TIM3_CH0B, TIM2_CHA, VC1_OUT, TIM4_CHB; analog: AIN7, VC0_INP11, VC0_INN7.
14 PB00 bidirectional GPIO PB00. Alt functions: PCA_CH2, TIM3_CH1B, TIM5_CHB, RCH_OUT, RCL_OUT, PLL_OUT; analog: AIN8, VC0_INN10, VC1_INN6.
15 PB01 bidirectional GPIO PB01. Alt functions: PCA_CH3, PCLK_OUT, TIM3_CH2B, TIM6_CHB; analog: AIN9/EXVREF (external ADC voltage reference), VC1_INP6, VC1_INN7.
16 DVSS power_in Digital and analog ground return (0V). Must be tied to system ground plane; the QFN32 also has DVSS at pin 32 and (typically) an exposed thermal pad that should be soldered to the ground plane.
17 DVCC power_in Digital supply (1.8-5.5V). Decouple to DVSS with 100nF ceramic near the pin plus bulk cap. Tie to AVCC on this package.
18 PA08 bidirectional GPIO PA08. Alt functions: UART0_TXD, TIM3_CH0A, TIM1_GATE, TIM4_CHA, TIM3_BK.
19 PA09 bidirectional GPIO PA09. Alt functions: UART0_TXD, TIM3_CH1A, TIM0_BK, I2C0_SCL, HCLK_OUT, TIM5_CHA.
20 PA10 bidirectional GPIO PA10. Alt functions: UART0_RXD, TIM3_CH2A, TIM2_BK, I2C0_SDA, TIM2_GATE, PCLK_OUT, TIM6_CHA.
21 PA11 bidirectional GPIO PA11. Alt functions: UART0_CTS, TIM3_GATE, I2C1_SCL, VC0_OUT, SPI0_MISO, TIM4_CHB.
22 PA12 bidirectional GPIO PA12. Alt functions: UART0_RTS, TIM3_ETR, I2C1_SDA, VC1_OUT, SPI0_MOSI, IR_OUT.
23 PA13/SWDIO bidirectional GPIO PA13 doubling as SWD data I/O (SWDIO). Alt functions: UART0_RXD, LVD_OUT, TIM3_ETR. Default after reset is SWDIO for debugger attach.
24 PA14/SWCLK bidirectional GPIO PA14 doubling as SWD clock (SWCLK). Alt functions: UART1_TXD, UART0_TXD, TIM3_CH2A, LVD_OUT, RCH_OUT, RCL_OUT, PLL_OUT. Default after reset is SWCLK.
25 PA15 bidirectional GPIO PA15. Alt functions: SPI0_CS, UART1_RXD, TIM0_ETR, TIM0_CHA, TIM3_CH1A.
26 PB03 bidirectional GPIO PB03. Alt functions: SPI0_CLK, TIM0_CHB, TIM1_GATE, TIM3_CH0A, XTL_OUT, XTH_OUT; analog: VC1_INN9.
27 PB04 bidirectional GPIO PB04. Alt functions: SPI0_MISO, PCA_CH0, TIM2_BK, UART0_CTS, TIM2_GATE, TIM3_CH0B; analog: VC0_INP12, VC1_INP12, VC1_INN10.
28 PB05 bidirectional GPIO PB05. Alt functions: SPI0_MOSI, TIM1_BK, PCA_CH1, UART0_RTS; analog: VC0_INP13, VC1_INP13.
29 PB06 bidirectional GPIO PB06. Alt functions: I2C0_SCL, UART0_TXD, TIM1_CHB, TIM0_CHA, TIM3_CH0A; analog: VC0_INP14, VC1_INP14.
30 PB07 bidirectional GPIO PB07. Alt functions: I2C0_SDA, UART0_RXD, TIM2_CHB, TIM0_CHB; analog: VC0_INP15, VC1_INP15, LVD_IN2.
31 PD03/BOOT0 bidirectional GPIO PD03, also serves as BOOT0 boot-mode select at reset. Sampled at power-on/reset to select between main Flash and system bootloader.
32 DVSS power_in Digital/analog ground return (0V). Second ground pin on the QFN32 in addition to pin 16; tie both to the board ground plane along with the exposed thermal pad.

Key specifications

Parameter Value
Manufacturer XHSC
Package QFN-32-EP(5x5)
Category MCU
Pins 32

Ordering variants

Same part, different packaging or reel option.

  • HC32F030F8UA-QN32TR
  • HC32F030F8UA-QN32TRF8TA
  • HC32F030F8UA-QN32TRE8PA
  • HC32F030F8UA-QN32TRJ8TA
  • HC32F030F8UA-QN32TRH8TA
  • HC32F030F8UA-QN32TRK8TA

CAD (KiCad official)

  • Symbol: HC32F030F8UA-QN32TR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XHSC datasheet (80 pp, sha256 c1f5c05168fa2ea7, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF