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Contents

README

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ADR4550ARZ-R7

Analog Devices · Voltage Reference · SOIC-8

ADR4550ARZ-R7 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NIC unconnected Internally not connected; the pin is not connected inside the device and is not specified for an external connection.
2 VIN power_in Input voltage connection; the ADR4550 electrical characteristics are specified for VIN = 5.1 V to 15 V, with a 16 V absolute maximum supply rating.
3 NIC unconnected Internally not connected; the pin is not connected inside the device and is not specified for an external connection.
4 GND power_in Ground reference for the device.
5 NIC unconnected Internally not connected; the pin is not connected inside the device and is not specified for an external connection.
6 VOUT power_out Buffered reference output that the datasheet rates for +10 mA source and −10 mA sink, and which should be wired directly to the load to preserve output accuracy.
7 NIC unconnected Internally not connected; the pin is not connected inside the device and is not specified for an external connection.
8 DNC unconnected Do not connect; this pin must be left unconnected by the user.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Initial output voltage error, grade A VOUT_ERR -0.04 0.04 % Grade A (ADR4550ARZ-R7) 9
Initial output voltage error, grade A VOUT_ERR 2 mV Grade A, absolute error 9
Solder heat shift (SHR) change -0.02 0.02 % After 3 reflow cycles 9
Temperature coefficient, grade A, box method TCVOUT 4 ppm/°C Grade A, −40°C ≤ TA ≤ +125°C (box method) 9
Temperature coefficient, grade A, bow-tie method TCVOUT 8 ppm/°C Grade A, −40°C ≤ TA ≤ +125°C (bow-tie method) 9
Line regulation ΔVOUT/ΔVIN 1 10 ppm/V −40°C ≤ TA ≤ +125°C 9
Load regulation, source ΔVOUT/ΔIL 25 80 ppm/mA IL = 0 mA to +10 mA source, −40°C ≤ TA ≤ +125°C 9
Load regulation, sink ΔVOUT/ΔIL 35 120 ppm/mA IL = 0 mA to −10 mA sink, −40°C ≤ TA ≤ +125°C 9
Supply current IQ 700 950 μA −40°C ≤ TA ≤ +125°C, no load 9
Dropout voltage, no load VDO 100 mV −40°C ≤ TA ≤ +125°C, no load 9
Dropout voltage, IL = 2 mA VDO 300 mV −40°C ≤ TA ≤ +125°C, IL = 2 mA 9
Ripple rejection ratio RRR 90 dB fIN = 1 kHz 9
Output current capability, sink IL -10 mA Sink current 9
Output current capability, source IL 10 mA Source current 9
Output voltage noise, peak-to-peak eNp-p 2.8 μV p-p 0.1 Hz to 10.0 Hz 9
Output voltage noise density eN 95.3 nV/√Hz 1 kHz 9
Thermal hysteresis, full cycle 25°C→+125°C→−40°C→25°C ΔVOUT_HYS -13 ppm Full cycle, +25°C to +125°C to −40°C to +25°C 9
Thermal hysteresis, half cycle 25°C→125°C→25°C ΔVOUT_HYS -97 ppm Half cycle, 25°C to 125°C to 25°C 9
Thermal hysteresis, full cycle 25°C→70°C→0°C→25°C ΔVOUT_HYS -8 ppm Full cycle, 25°C to 70°C to 0°C to 25°C 9
Thermal hysteresis, half cycle 25°C→70°C→25°C ΔVOUT_HYS -17 ppm Half cycle, 25°C to 70°C to 25°C 9
Long-term drift, early drift ΔVOUT_LTD 19 ppm TA = 25°C, 250 hours 9
Long-term drift ΔVOUT_LTD 25 ppm TA = 25°C, 1000 hours 9
Long-term drift ΔVOUT_LTD 51 ppm TA = 25°C, 4500 hours 9
Turn-on settling time tR 160 µs COUT = 0.1 µF, CIN = 0.1 µF, RLOAD = 1 kΩ 9
Load capacitance 0.1 100 µF 9
Input voltage VIN 5.1 15 V ADR4550 specified input range 9
Maximum supply voltage VIN 16 V 10
Operating temperature range TA -40 125 °C 10
Storage temperature range TSTG -65 150 °C 10
Junction temperature range TJ -65 150 °C 10
ESD, human body model 6 kV HBM 10
Thermal resistance, junction-to-ambient θJA 120 °C/W 8-lead SOIC, 2-layer JEDEC board 10
Thermal resistance, junction-to-case θJC 63 °C/W 8-lead SOIC, 1-layer JEDEC board, 100 µm TIM 10

CAD (KiCad official)

  • Symbol: ADR4550ARZ-R7
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: adr4550arz-r7-etched.step / adr4550arz-r7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adr4550arz-r7.step / adr4550arz-r7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (37 pp, sha256 48d4d0fe0ae23886, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF