component
AP7354-33W5-7
Public Made by Adomby adom
Diodes Incorporated Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-25. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownAP7354-33W5-7
Diodes Incorporated · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-25
AP7354-33W5-7 from Diodes Incorporated, in a SOT-25. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Power input; the datasheet specifies an input voltage range of 2.0 V to 5.5 V, and a minimum 0.1 µF ceramic capacitor is recommended between VIN and GND. |
| 2 | GND | power_in | Ground; the regulator GND pin must be connected to the external circuit ground to limit trace-impedance voltage drop. |
| 3 | EN | input | Chip enable that must be driven high or low and must not float; high (minimum 1.0 V, maximum 5.5 V) enables the output, low (maximum 0.4 V) puts the regulator in shutdown, and the absolute maximum rating is 6.0 V. |
| 4 | NC | unconnected | No connection on the SOT25 package according to the pin assignment figure ("EN NC"); this pin is not listed in the pin description table. |
| 5 | VOUT | power_out | Regulated output voltage, which is 3.3 V for this part, with a guaranteed output current of 150 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-25 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | 2 | 5.5 | V | TA = -40°C to +85°C | 4 | ||
| Output Voltage Accuracy (VOUT > 2.0V) | -1 | 1 | % | VOUT > 2.0V, IOUT = 1mA, TA = +25°C | 4 | ||
| Output Voltage Accuracy (VOUT > 2.0V) | -2 | 2 | % | VOUT > 2.0V, IOUT = 1mA, TA = -40°C to +85°C | 4 | ||
| Line Regulation (∆VOUT/∆VIN/VOUT) | ∆VOUT/∆VIN/VOUT | 0.02 | 0.1 | %/V | MAX (VOUT + 1.0V, 2.5V) ≤ VIN ≤ 5.5V (All Versions Except 4.5V) | 4 | |
| Load Regulation (∆VOUT) | ∆VOUT | -40 | 40 | mV | 1mA ≤ IOUT ≤ 150mA (All Versions Except 4.5V) | 4 | |
| Quiescent Current | 0.25 | 0.6 | µA | IOUT = 0mA | 4 | ||
| Standby Current | ISTANDBY | 0.02 | 0.2 | µA | Set EN Low, No Load | 4 | |
| Dropout Voltage | 0.16 | 0.35 | V | IOUT = 150mA, VOUT = 3.3V | 4 | ||
| EN Input Low Voltage | 0.4 | V | 4 | ||||
| EN Input High Voltage | 1 | 5.5 | V | 4 | |||
| Input Voltage | VIN | 2 | 5.5 | V | 3 | ||
| Output Current | IOUT | 0 | 150 | mA | 3 | ||
| Operating Ambient Temperature | TA | -40 | 85 | °C | 3 | ||
| Input Voltage | VIN | 6 | V | 3 | |||
| Input Voltage at EN Pin | VEN | 6 | V | 3 | |||
| Output Voltage to GND | VOUT | -0.3 | V | Printed as -0.3 to VIN +0.3 V; upper limit depends on VIN and is not a fixed number | 3 | ||
| Operating Ambient Temperature | TA | -40 | 85 | °C | 3 | ||
| Maximum Junction Temperature | TJ | 125 | °C | 3 | |||
| Storage Temperature | TSTG | -55 | 125 | °C | 3 | ||
| Power Dissipation | PD | 315 | mW | Note 6: based on application temperature of +40°C; derate 3.75mW per °C above +40°C | 3 | ||
| ESD Protection, Human Body Model | ESD HBM | 4 | kV | 3 | |||
| ESD Protection, Machine Model | ESD MM | 400 | V | 3 | |||
| Thermal Resistance Junction-to-Ambient (SOT25) | ΘJA | 162 | °C/W | Note 11: device mounted on 1" × 1" FR-4 MRP substrate PCB, 2oz copper, minimum recommended pad layout | 4 | ||
| Thermal Resistance Junction-to-Case (SOT25) | ΘJC | 38 | °C/W | Note 11: device mounted on 1" × 1" FR-4 MRP substrate PCB, 2oz copper, minimum recommended pad layout | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Terminals: SOT23/SOT25: Finish - Mate Tin Plated Leads, Solderable | 1 |
CAD (KiCad official)
- Symbol:
AP7354-33W5-7 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-25 (KiCad packages3D, STEP)
- 3D model files:
ap7354-33w5-7-etched.step/ap7354-33w5-7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ap7354-33w5-7.step/ap7354-33w5-7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (18 pp, sha256
3d9ef71ba1cf3e6f, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).