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Oliver's LED Nameplate

A USB-C powered desk nameplate that spells OLIVER in 57 white 0603 LEDs. Plug in any phone charger and the name lights up.

Built with tscircuit on a 4-pin Adom molecule, previewed with adom-tsci, then round-tripped through KiCad 10 (.kicad_pcb) and Fusion 360 (STEP) to confirm the geometry survives the trip.

Specs

Board 178 x 58 mm, 2-layer, roundEdges={false}
Molecule type="4pin", pinType="MachinePinLargeStandard"
LEDs 57 white 0603 (O=12, L=7, I=9, V=9, E=10, R=10)
Font 3x5 pixel dot-matrix, 6 mm pitch, 8 mm letter gap
Current limiting 57 x 330 ohm 0603, one per LED (~5.5 mA each)
Power in USB-C TYPE-C-31-M-12 (JLCPCB C165948), east edge
CC pulldowns 2 x 5.1k on CC1/CC2
Bypass 100 nF 0603 on VBUS
Total draw ~310 mA @ 5 V

Verified

  • 185 / 187 traces routed. KiCad 10 reports Unrouted 0 — 951 track segments, 55 vias, 61 nets, 264 pads.
  • USB-C geometry lint passes: body_fwd = 5.34 mm, mouth exits the board edge at x = 89.2 mm, so a cable actually seats.

Two gotchas worth stealing

1. USB-C pin labels must be unique. The wrapper this was forked from labelled two different pins GND1 (pin1 + pin15) and two VBUS1 (pin3 + pin13). tscircuit merges same-labelled ports into one pcb_port, so their pads land on top of each other:

pcb_pad_pad_clearance_error: Pads J1>GND1 and J1>GND2 too close (0mm, min 0.1mm)
pcb_autorouting_error: Autorouting was skipped because 4 PCB placement errors were found

The board then silently ships completely unrouted. Fix: unique labels (GND_A1, GND_B12, GND_A12, GND_B1, VBUS_A4, VBUS_B9, VBUS_A9, VBUS_B4) tied together with traces.

2. Never trace a USB-C pin by number. <trace from="J1.pin3" .../> makes tsci build hang forever with no output and no CPU (it blocks, it doesn't spin). Always trace by label: <trace from="J1.VBUS_A4" .../>.

Also: a receptacle wrapper MUST forward schX/schY/schRotation to its inner <chip>, or it silently piles at the schematic origin.

Known limitation

MP1..MP4 — the Molecule library's internally-emitted machine pins — still overlap at the schematic origin. They can't be placed from board source; the rest of the layout is lifted clear to compensate.