OCuLink Riser for the Supermicro AIOM Slot

@@ -6,6 +6,8 @@ The whole build, filmed off the screen while Claude worked in Adom Hydrogen, cut |---|---|---| | [1. The request and the research](#1-the-request-and-the-research) | 0:00 to 0:46 | The prompt, the OCP 3.0 and OCuLink specs, the aiflow timeline, the 85 ohm field solver | | [2. Routing the high-speed lanes](#2-routing-the-high-speed-lanes) | 0:52 to 1:38 | The netlist, 36 differential pairs routed and length-tuned, the slow-net router, the connector model |+| [3. Design rule check and the design record](#3-design-rule-check-and-the-design-record) | 1:38 to 2:25 | KiCad DRC, fixes at the source, a pause to ask before taking over the screen, skew results |+| [4. Scan chain, parts and sourcing](#4-scan-chain-parts-and-sourcing) | 2:25 to 3:12 | The router converging, the outline fix, the OCP scan chain, new component pages, live stock |  ## 1. The request and the research @@ -31,3 +33,27 @@ The whole build, filmed off the screen while Claude worked in Adom Hydrogen, cut - Its clearance check finds two near misses between a reference clock pair and a transmit lane; it moves a via and re-checks until they are gone. - A multi-layer maze router takes the slow nets (power, ground, resets, the scan chain) in the background. - It writes the KiCad 10 schematic generator and models the OCuLink receptacle from the Amphenol drawing, labelled as AI-generated, since no vendor 3D model exists.++## 3. Design rule check and the design record++<video controls preload="metadata" width="1080" poster="clips/clip-03-poster.jpg" src="clips/clip-03.mp4"></video>++[Download clip 3](clips/clip-03.mp4) (2 min 53 s, 16x, narrated)++- Every slow net routes with zero failures; the grounds are fanned out, the planes stitched, and KiCad's own DRC runs on the result.+- The first DRC finds clearances, duplicate vias, a short near the ESD parts and courtyard overlaps; each is fixed in the generator, not patched on the board.+- The run pauses on a question: the next stages draw the copper live in KiCad on this computer and film it, so Claude asks first. The answer (go ahead, on this box, now) comes about 15 minutes later.+- Local routing for the ESD grounds, and via placement that keeps a safe hole-to-hole distance from every plated hole.+- The design record: impedance per layer, delay matching per port, the present-pin encoding and the power-good timing. Skew inside each pair is at most 0.017 mm against the spec's 0.127 mm.++## 4. Scan chain, parts and sourcing++<video controls preload="metadata" width="1080" poster="clips/clip-04-poster.jpg" src="clips/clip-04.mp4"></video>++[Download clip 4](clips/clip-04.mp4) (2 min 53 s, 16x, narrated)++- The rip-up router converges, one stuck net fewer each round.+- The DRC list narrows to recurring issues; a malformed outline (tiny arc stubs at the corners) is fixed in the outline generator and the pipeline re-runs.+- The SN74LV165A shift register is the card's OCP 3.0 scan chain: the card reports what it is to the server over it, which a bare passive adapter would miss.+- Two parts get new Adom wiki component pages, including the OCuLink receptacle, with a provenance record marking which files are AI-generated.+- Live Mouser and DigiKey stock checks for the new capacitor and the status LED, and a bill of materials of orderable parts.

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