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OCuLink Riser for the Supermicro AIOM Slot
Public Unreviewedby John Lauer
Passive OCP NIC 3.0 SFF card that breaks a Supermicro AIOM slot's PCIe x16 into four OCuLink 4i ports (4 x4, Gen4): 6-layer, 85 ohm, length-matched, DRC-clean KiCad project with Gerbers, BOM and CPL.
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Clip 2: routing the high-speed lanes
3 files changed
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clips/README.md+14@@ -5,6 +5,7 @@ The whole build, filmed off the screen while Claude worked in Adom Hydrogen, cut | Clip | Real time | What happens | |---|---|---| | [1. The request and the research](#1-the-request-and-the-research) | 0:00 to 0:46 | The prompt, the OCP 3.0 and OCuLink specs, the aiflow timeline, the 85 ohm field solver |+| [2. Routing the high-speed lanes](#2-routing-the-high-speed-lanes) | 0:52 to 1:38 | The netlist, 36 differential pairs routed and length-tuned, the slow-net router, the connector model | ## 1. The request and the research @@ -17,3 +18,16 @@ The whole build, filmed off the screen while Claude worked in Adom Hydrogen, cut - It finds the Amphenol OCuLink receptacle drawing and the 168-pin edge layout, including the present and bifurcation pins that tell the server how to split the x16 link. - The adom-aiflow timeline opens: the clock starts at the prompt, and every gate from design rules to Gerbers is listed. - It writes a small 2D field solver for 85 ohm differential pairs on a 6-layer stackup, then checks the card outline and keep-out zones against the spec drawings.++## 2. Routing the high-speed lanes++<video controls preload="metadata" width="1080" poster="clips/clip-02-poster.jpg" src="clips/clip-02.mp4"></video>++[Download clip 2](clips/clip-02.mp4) (2 min 53 s, 16x, narrated)++- The design becomes data first: 51 components, 109 nets and 418 connected pins in a netlist.+- Claude routes the 36 high-speed differential pairs with its own router, from the gold fingers to the OCuLink connectors with no crossings.+- Accordion bumps tune each lane's length so the lanes in a port match to within 0.01 ps.+- Its clearance check finds two near misses between a reference clock pair and a transmit lane; it moves a via and re-checks until they are gone.+- A multi-layer maze router takes the slow nets (power, ground, resets, the scan chain) in the background.+- It writes the KiCad 10 schematic generator and models the OCuLink receptacle from the Amphenol drawing, labelled as AI-generated, since no vendor 3D model exists.
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