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Diode-Bridge Voltage-Controlled Attenuator

Public Unreviewed

by John Lauer

Two-layer through-hole audio attenuator: four 1N4148s as a current-biased shunt bridge, 0 to 2 V control, designed by Saif Abdessayed with Adom Hydrogen

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John Lauer Saif Abdessayed's diode-bridge VCA: KiCad project, Gerbers, BOM, simulations, reports, and the earlier RC filter test 45f3ff6 11d ago

Engineering review: diode-bridge voltage-controlled attenuator

Outcome

This is a complete prototype design for an externally powered, analog, diode-based voltage-controlled attenuator. The board takes regulated +12 V / GND / -12 V at J1. It does not synthesize or regulate those rails on-board because no upstream voltage, dissipation allowance, or regulator headroom was specified. If “regulated ±12 V supplies” was intended to require on-board regulators, that remains an interface requirement needing an input-supply specification; it was not silently guessed.

At 100 mVpp and 1 kHz, actual ngspice runs give gain 0.968 at 0 V control and 0.1547 at 2 V control, or 15.93 dB attenuation relative to 0 V. The five simulated control points are monotonic. At 12 Vpp the diode junctions are driven far outside the small-signal regime: the model predicts only about 0.83 dB relative attenuation at 2 V control and 5.69% THD. This prototype therefore meets the stated small-signal attenuation test but must not be represented as providing the same attenuation at maximum input.

No physical board has been built or measured. Component spread, temperature, diode matching, PCB parasitics, and TL072 non-ideal distortion need bench validation.

Chosen topology

Four 1N4148 diodes form a symmetric, current-biased shunt bridge between two bipolar coupling capacitors. A TL072CP section buffers the input. The second section servos a 2N3904 emitter current so bridge bias is approximately VCTRL / 8.06 kOhm. The bridge is fed from +12 V through 22 kOhm; a 2.2 kOhm series output resistor and the specified 100 kOhm onboard load define the unattenuated path.

This topology was selected because the anti-symmetric diode bridge cancels most audio-frequency bias voltage at the signal ports, allows continuously controlled shunt resistance, and uses only hand-solderable through-hole parts. It also exposes the fundamental limitation honestly: once audio voltage is large compared with diode thermal voltage, attenuation and distortion become signal-level dependent.

No envelope detector, comparator, LED/display circuit, or makeup-gain stage is present.

Manufacturer and sourcing evidence

Sourcing counts in the BOM are snapshots, not reservations. Recheck inventory and lifecycle before purchasing.

Calculations (not simulation)

With the bridge effectively off, the ideal loaded divider is:

A0 = 100 kOhm / (100 kOhm + 2.2 kOhm) = 0.9785.

The servo target currents are:

Control Calculated bridge current
0 V 0 uA
0.5 V 62.0 uA
1.0 V 124.1 uA
1.5 V 186.1 uA
2.0 V 248.1 uA

Using the compact-model emission coefficient n = 1.906, the bridge’s rough small-signal shunt resistance is 2 n VT / I, giving approximately 1.59 kOhm, 795 Ohm, 530 Ohm and 397 Ohm at 0.5, 1.0, 1.5 and 2.0 V. Combining those values with 2.2 kOhm predicts gains near 0.416, 0.264, 0.193 and 0.152. These are engineering estimates; device matching and temperature dominate the real result.

For a 12 Vpp sine at 20 kHz, required slew rate is 2 pi f Vpk = 0.754 V/us, below the TL072CP’s 13 V/us typical figure. The nominal output peak is 6 V, leaving supply headroom on ±12 V rails. These are datasheet estimates, not distortion guarantees.

Actual ngspice results

The retained simulation uses ngspice 42, compact 1N4148/2N3904 models, exact passives, an ideal unity-gain audio buffer, and a high-gain limited control servo. Therefore results characterize the diode network and control law; they do not model every TL072 distortion mechanism.

1 kHz transient results

Control Input Vout pp Gain THD
0 V 0.1 Vpp 0.09684 Vpp 0.9684 0.1587%
0.5 V 0.1 Vpp 0.04186 Vpp 0.4186 0.2598%
1.0 V 0.1 Vpp 0.02667 Vpp 0.2667 0.1264%
1.5 V 0.1 Vpp 0.01957 Vpp 0.1958 0.0735%
2.0 V 0.1 Vpp 0.01547 Vpp 0.1547 0.0478%
0 V 12 Vpp 11.238 Vpp 0.9365 1.972%
0.5 V 12 Vpp 10.967 Vpp 0.9139 2.396%
1.0 V 12 Vpp 10.714 Vpp 0.8928 3.299%
1.5 V 12 Vpp 10.462 Vpp 0.8719 4.437%
2.0 V 12 Vpp 10.211 Vpp 0.8509 5.694%

The 0 V gain requirement is satisfied for the documented 100 mVpp small-signal test. At 12 Vpp the modeled 0 V gain is 0.9365, outside 0.95–1.05; because the original requirement did not state the 0 V test amplitude, this is explicitly unresolved if the tolerance was intended to apply at full scale.

AC response

Control 20 Hz 1 kHz 20 kHz
0 V -0.2733 dB -0.2733 dB -0.2736 dB
0.5 V -7.6289 dB -7.6359 dB -7.6359 dB
1.0 V -11.4873 dB -11.5191 dB -11.5191 dB
1.5 V -14.1148 dB -14.1886 dB -14.1886 dB
2.0 V -16.1016 dB -16.2341 dB -16.2342 dB

The retained mismatch run gives 87.997 mV peak output feedthrough for an intentionally fast 0-to-2 V, 1 ms control ramp with D4 saturation current 2% high and zero audio input. This is a pessimistic model experiment, not a measured specification. Slower external control and closer diode matching should reduce it.

PCB verification

  • Board outline: 58 mm × 40 mm; two copper layers.
  • Routed track width: 0.50 mm everywhere, above the provisional 0.25 mm minimum.
  • Copper clearance rule: 0.20 mm minimum.
  • Signal/power vias: 0.60 mm diameter / 0.30 mm drill.
  • Explicit ground traces connect every GND pad; a bottom GND pour is also present.
  • Final KiCad 10.0.6 ERC: 0 errors, 0 warnings.
  • Final board/schematic parity lint: 0 errors, 0 warnings.
  • Final zone-refilled DRC: 0 errors, 1 warning, 0 unrouted, 0 exclusions.
  • Remaining DRC warning: KiCad reports one isolated fragment in the bottom GND fill. It does not carry a required connection; all GND pads have explicit routed connectivity. It was left visible rather than excluded.
  • Connector polarity and silkscreen: J1 is +12 / GND / -12; J2 and J4 are signal/GND; J3 is control/GND. C7’s positive lead goes to GND because its negative lead is on -12 V.

The stated design rules are provisional tests only. No fabricator stack-up, annular-ring, solder-mask, silkscreen, or panel rules have been approved.

Unresolved issues and prototype tests

  1. Confirm whether regulated rails are supplied externally as designed. On-board regulation cannot be added responsibly without the raw input range and thermal budget.
  2. Bench-check gain and monotonicity at 100 mVpp, 1 kHz, at all five control voltages.
  3. Sweep THD+N and gain versus input amplitude through 12 Vpp. Expect attenuation collapse and rising distortion at high level.
  4. Measure control feedthrough with the intended control-source impedance and edge rate.
  5. Characterize temperature and diode-lot spread. Populate D1–D4 from one lot; matching is not guaranteed by the 1N4148 ordering code.
  6. Confirm the external 100 kOhm load convention. The board already includes R4 = 100 kOhm, so an additional external 100 kOhm would create a 50 kOhm effective load.
  7. No EMC, safety, thermal, ESD, or physical manufacturing validation has been performed.

Requirement status

The small-signal electrical targets, frequency range, diode control method, monotonicity, hand-solderable construction, exclusions, board-size/routing rules, and file deliverables are met by calculation, simulation and KiCad checks. Physical performance, full-scale 0 V gain tolerance, and any interpretation requiring on-board rail regulation remain unverified as stated above.