12 V to 5 V / 1 A Buck Molecule (TPS54202)

@@ -1,138 +0,0 @@-# adom-aiflow gap log: 12 V → 5 V / 1 A buck molecule run--> Publishing rule: this log feeds public issues/PRs. Name the fab only as "3rd party fab".--Every step of this run that adom-aiflow did not guide, gate or measure, recorded as it happened, so each can become an issue or PR on adom/adom-aiflow.--Proposed direction (John's question, 2026-09-29): keep the binary as **instrument** (ledger, clock, capture, compose), **gates** (checks that refuse) and **hands** (native landing through the bridge). Move the engineering judgement (what to build, which parts, which steps, placement, routing strategy, spec) into skills the AI reads. Each gap below is tagged with where it belongs:--- **skill**: judgement or policy the AI should follow.-- **gate**: a deterministic check the binary should enforce.-- **instrument**: something the binary should measure or record.--| # | Step | What happened without aiflow | Belongs in |-|---|------|------------------------------|------------|-| 1 | Clock before the board | `start` needs a `.kicad_pcb`, so requirements, part choice, calculations, simulation and the schematic (the first hour or more) are untimed. The clock should start at the prompt with no board. | instrument |-| 2 | Requirements intake | Pulled the brief (12 V in, 5 V / 1 A out, terminals, test points) out of a YouTube video by hand, using yt-dlp and ffmpeg frame sampling. There is no intake step that turns a brief into a requirements file. | skill |-| 3 | Sourcing policy | John: build on a 3rd party fab, so source from Mouser, not JLCPCB. The fab target should pick the sourcing profile: 3rd party fab = Mouser + Adom basic parts (PnP reels), no JLCPCB parts; JLCPCB fab = JLCPCB/LCSC parts, kept as a user option. aiflow should suggest this, not wait for the human to say it. | skill + gate (BOM available at Mouser) |-| 4 | Parts-search analysis | IC shortlist and stock check done ad hoc (TPS54202: Mouser 160 in stock, 140-day lead; DigiKey 0; JLC 180k). There is no guided "what will you need, where does it come from" pass. | skill + gate |-| 5 | Adom basic parts first | Passive values constrained to the 41 stocked resistor values and stocked MLCCs (the feedback divider needed a series pair to hit 5 V). Nothing in aiflow points at adom-basic-parts or pnp-inventory. | skill + gate (flag non-stocked passives) |-| 6 | Datasheet calculations | L, COUT, CIN, feedback divider, feed-forward cap and EN UVLO derived by hand from the datasheet equations. There is no step that records the design equations next to the values. | skill (+ instrument: calcs as an artifact) |-| 7 | Simulation | ngspice was not installed; installed it. No simulation step or gate (startup, load step, ripple, loop gain). | skill + gate |-| 8 | Schematic + netlist to board | No path from a schematic to a netlisted `.kicad_pcb`; the KiCad bridge has no "update PCB from schematic" verb. Generated both from one netlist and checked equivalence. | gate (sch↔pcb netlist equivalence) |-| 9 | Molecule format | John: "make sure you make a molecule". aiflow does not know about molecules (machine pins, contacts, outline grid). | skill + gate (molecule conformance) |-| 10 | Fab design rules | aiflow's DRC uses the board's own rules; nothing loads the target fab's process limits (3rd party fab or JLCPCB profile). | gate |--## Skills this run will add to adom/adom-aiflow `skills/`--Each is written from what this run actually did, when that phase ends. The binary keeps only instrument, gate and hands work.--| Skill | Covers gaps | Status |-|-------|-------------|--------|-| `aiflow-intake` | 1, 2: brief → `requirements.json` (inputs, outputs, form factor, fab target, deliverables); start the clock at the prompt, before any board exists | planned |-| `aiflow-sourcing` | 3, 4, 5: fab target picks the sourcing profile (3rd party fab: Mouser + Adom basic parts, no JLCPCB parts; JLCPCB: JLCPCB/LCSC parts); the parts-search pass; stocked-value constraints | planned |-| `aiflow-circuit-design` | 6, 7: datasheet equations as a script next to the values; ngspice loop gain + switching transient; how to label a fitted model honestly | planned |-| `aiflow-schematic-to-board` | 8: one netlist → `.kicad_sch` + `.kicad_pcb`, ERC, netlist equivalence | planned |-| `aiflow-molecule` | 9, 10: molecule outline, machine pins, contacts, fab rules profile | planned |--## Findings to fold into the skills--- **Sourcing: search by spec, in stock, before naming an MPN.** Remembered first choices (Coilcraft XAL5050-153, Murata GRM31CR71E106KA12L) had zero Mouser stock with 180 to 280 day leads. `adom-parts-search search "<spec words>" --in-stock-only` found equivalents at once. The sourcing skill should make the spec search the first move and record stock + lead with a date in the BOM.-- **Stocked passives shape the math.** The 41-value resistor set forced a series pair (68k + 5.6k) for the feedback divider; the calcs script searches stocked combinations instead of assuming E96.-- **Simulation without a vendor model.** TI's internal compensation is unpublished, so the loop model is an equivalent calibrated to the datasheet's own crossover equation (eq 14), labelled as such. The two-model split worked: an averaged AC model for loop gain and a cycle-by-cycle XSPICE latch model for startup, ripple and load steps. The switching model matched the hand calcs (ripple current 0.40 vs 0.39 A). ngspice syntax traps worth a line in the skill: B-source logic is `||`/`&&`; `d_srlatch` needs enable + async set/reset (NULL); `wrdata` phase is radians; system matplotlib needs `PYTHONNOUSERSITE=1` when a user-site numpy 2 is present.-- **Model limits decide, not the prettiest number.** 100 pF Cff (eq 16) gave the best phase margin in the model but pushed crossover to ~57 kHz, past the datasheet's 40 kHz limit that the equivalent model can't see; 68 pF was chosen. The skill should say: when a fitted model and a datasheet limit disagree, obey the limit and plan a bench check (here: a real load step).--## Later gaps--| # | Step | What happened without aiflow | Belongs in |-|---|------|------------------------------|------------|-| 12 | Vendor-model simulation (PSpice) | John: the run must do a PSpice simulation, matching the brief's workflow. aiflow has no simulation step at all. Needed: a `simulate` step with two engines: ngspice (container, fitted models, always available) and PSpice for TI on a Windows box via Adom Bridge (vendor transient model, which carries the internal compensation a fitted model can't see). Results (startup, ripple, load step, loop) land in the run as artifacts; the gate compares them against requirements.json. | skill + gate + hands (bridge-driven PSpice batch run) |-| 13 | Vendor logins | I asked John for his TI login. He: "go get my login on your own… make sure adom-aiflow helps you know how to go get my credentials so you never have to ask". The skill must carry the ladder: `pup_credentials` → `pup_login` from the vault; not there → `pup_import_browser_logins {hostFilter}` (the user's own saved Chrome/Edge logins, one consent); saved on another desktop → `pup_vault_sync {peer}`; stale → the browser-password-manager recovery in pup-credentials. Never ask the human for a password. | skill |-| 14 | Vendor accounts via the real browser | TI sign-up/sign-in only worked in John's own Chrome through nb (pup's browser got a press-and-hold bot check that a human click could not clear). What worked: nb window in the user's profile → fill forms → hand any human-verification step to the user as one ready click → read verification codes from Gmail with `adom-google api gmail.googleapis.com/...` → type passwords with trusted keystrokes (`nbrowser_type` into the focused field; TI's `ti-password`/`ti-input` web components ignore programmatic value sets). The skill should say: vendor sign-up/sign-in = nb first; shadow-DOM form components need focus + real typing. | skill |-| 15 | PSpice for TI access | Request → export approval (minutes to 24–48 h) before download. TI's "Unencrypted PSpice Transient Model Package" for TPS54202 is Cadence-encrypted (`$CDNENCSTART`), so only PSpice runs it; ngspice cannot. The simulate step must plan for an approval wait and fall back to ngspice results meanwhile. | skill |-| 16 | pup crash on secrets | `credential_set` and `pup_type` carrying a password drop the pup bridge on both boxes (HTTP error to its local port), while read verbs work. File on adom/pup-bridge. | bug report |-| 17 | send_files to a `.pretty` dest | `send_files {dest:".../x.pretty"}` wrote a FILE named x.pretty (or returned `target_not_found`) instead of a folder, so KiCad footprint libraries can't be pushed directly. Workaround: send to a plain folder, `move` into place. File on adom/adom-bridge. | bug report |-| 18 | No chipsmith | John: "don't use chipsmith anymore. put that rule into adom-aiflow and the skills". The components/models skills must say: never use adom-chipsmith; model sources in order are the wiki component page's validated STEP, a redistributable manufacturer STEP, then a model generated from datasheet dimensions (OpenCascade/OCP script, labelled AI-created with provenance), always verified in the native EDA 3D viewer. | skill (+ flow file hints) |-| 19 | STEP generation route | I installed OCP (OpenCascade for Python + VTK) locally to model the inductor. John: use the shared step2glb OCCT service (`/create-chip`, `/create-footprint`, `/bake`, `step2glb convert/features`); install OCCT locally only when that service is persistently unreachable. The models skill should say this, with `step2glb health` as the first check. | skill |-| 20 | Sourcing order was in the hints and I skipped it | adom-aiflow's components hints already say: manufacturer site → distributors (Mouser/DigiKey links) → pup when blocked → generate only then. I drew the inductor from the datasheet before looking; Abracon publishes an official STEP (found only by searching the SERIES `AMPLH5030S`, not the full ordering code) and Panasonic publishes case-size STEPs (DS_Alumi_<case>). Lesson for the skill: search the manufacturer by series as well as by full MPN; vendor sites 403 curl, so go straight to pup/nb; three of the found models were Y-up (Abracon, Panasonic, and the wiki's Samsung 0805), so `step2glb features` must run on every model and a -90 X rotation be verified in the native 3D view. Also: I had written the electrolytic's case size into the BOM from memory; the model search forced the check (Panasonic page: 6.3 x 5.8 mm, code D). Never write a package dimension without its source. | skill + gate (every model: features bbox vs footprint, Z-up) |-| 21 | No native kicad-cli in the container | aiflow's DRC needs a native kicad-cli whenever the board has project rules (.kicad_pro/.kicad_dru); the container's /usr/bin/kicad-cli is KiCad 7 (no `pcb drc`, can't read a KiCad 10 board) and `place check` failed. Built `tools/kicad-cli-remote`: `ADOM_AIFLOW_KICAD_CLI` wrapper that ships the board + project files to the desktop's KiCad 10 via Adom Bridge, runs `kicad-cli pcb drc`, pulls the JSON back (about 5 s a round trip). Should ship with aiflow (or the KiCad bridge should expose a `kicad_cli_drc` verb) and `start --target` should set it up by itself. | instrument/gate (PR) |-| 22 | Stale kicad-cli wins silently | Another session in this container ran `apt-get install kicad` (Ubuntu 24.04 stock 7.0.11) at 20:24; aiflow's run_drc takes any `kicad-cli` whose `--version` succeeds, so KiCad 7 (no `pcb drc`, can't read a KiCad 10 board) broke the gate with a usage error. aiflow should read the board's file version, require a kicad-cli that can open it, and say "set ADOM_AIFLOW_KICAD_CLI (or use the bridge's KiCad)" instead of failing obscurely. | gate (PR) |-| 23 | `land route` is not resumable | The KiCad bridge dropped one reply (HTTP error to its local port) at trace 35 of 48. The live revision proved trace 35 had not landed, but `land route` has no `--from` and no dedupe (vias have one), so a rerun would duplicate traces 1-34. Built a resume plan by hand (flattened traces 35-48). aiflow should skip traces already on the live board (same net, same points) like `land vias`, and retry once on a transport error after checking the revision. | hands (PR) |-| 24 | Duplicate Kelvin keepout names | `pour` names every Kelvin tap keepout segment `Kelvin tap keepout {net}` (crates/aiflow-pours/src/lib.rs:184); a net with several segments gives duplicates (here 7 VOUT + 10 GND) and KiCad Bridge's zone plan refuses them ("every planned zone requires a unique nonempty name"), with the refusal reason hidden behind `zone_plan_refused {}` in the CLI error. Fix: number per net (`... {net} #{k}`), and print the bridge's `error` text in the ERROR line. Worked around by renumbering run/plan-pours.json. | bug (PR) |-| 25 | Router has no layer policy for 2-layer power boards | The grid router used B.Cu as free space: 17.5 mm of VOUT and 2.8 mm of FB under the hot loop (U1, input caps), plus the VOUT Kelvin sense sliced the bottom GND plane under C2/C4. Nothing in the spec can say "B.Cu is the ground plane under this region". Needed: a spec field (e.g. `planeUnder: {"layer":"B.Cu","region":[...],"nets":["GND"]}`) that the router treats as a keepout for other nets, and a gate that reports signal copper under the hot loop. Reworked FB and VOUT by hand (take route partially = ai). | skill + router (PR) |-| 26 | Packer picks rotations that knot a divider chain | `place pack` chose 90/270 per part independently; R1/R2/C9 ended VOUT-bottom/FBM-top, forcing FBM to loop around and the router to put a via inside an 0402 pad (solder-wicking risk). Rotating the three 180 deg made the chain read VOUT-R1-FBM-R2-FB top to bottom (FBM became a 1 mm straight link). The placement skill should say: for series chains, give ONE rotation, or have pack score shared-net pad adjacency. | skill (+ pack scoring PR) |-| 27 | Kelvin keepouts on both layers and at the power pin | Kelvin tap keepouts are emitted on F.Cu+B.Cu for every segment, and right up to the power pin (U1.1 GND): they fenced U1's GND pin off from the ground pour (its main heat path) and slotted the bottom plane. Keepouts should follow the sense segment's own layer and stop short of the pin they tap. | bug (PR) |-| 28 | Thermal vias for small pins land in the pad | `pour` places `thermalVias` only at offsets inside the pad (half-length − 0.4 mm); a SOT-23 pin has none, so it falls back to ONE 0.8 mm via in the pad centre (open via-in-pad wicks solder on a 0.6 × 1.1 mm pad) and ignores `count`. For small pins, place the vias in the solid pour just outside the pad, at 0.6/0.3, clear of other nets; honour `count` or say why not. Overrode plan-vias.json by hand here. | bug (PR) |-| 29 | A planned GND via landed as SW | `land vias` placed two "GND" thermal vias whose pads touched the router's SW trace; KiCad/the bridge assigned them to SW and the DRC check passed, so the landing reported success. The via's planned net must be enforced (refuse if its copper touches another net). Also: the manifest lost clip files (placement/routing entries show file None, components clip missing from disk). | bug (PR, bridge + aiflow) |-| 30 | Live clips sub-readme | John: "make sure adom-aiflow talks about how to always append to an ongoing sub-readme as the ai works … so that the user can follow along in a pup tab or webview tab of the video clips as the ai builds … when the ai runs all night, the user expects to wake up to a whole bunch of new video clips." The run README exists but has no clip list; clips aren't published as they land. aiflow should append every stopped clip (10x cut, contact sheet, step, what it shows, suspect state) to `docs/clips.md` on the page and push it at each step change, and the skill should tell the AI to open that tab for the user once. | instrument + skill |-| 31 | `tour fields` on the wrong box | In an Adom Hydrogen desktop container VSCODE_PROXY_URI is `http://{{port}}.localhost:<port>/`, reachable only on the machine hosting the container; `tour fields` opened it on the test box (ConfRoomROG) and got an error page ("the app's window did not appear"). When the proxy is a localhost URL, aiflow should film on the container's host (or say so and name `--on`). Worked around with `tour fields --on AdomLapper`. | bug (PR) |-| 32 | Silkscreen text verb contract | `kicad_silk_text_batch` takes `width`, `height`, `stroke` (not size/thickness), mirrors B.SilkS by itself and refuses a `mirror` field; its dry run refuses NEW text below the board's minimum text height as an error (text_height), so the silkscreen doc's 0.5/0.3/0.2 mm value sizes are unreachable unless the board's min text height is lowered first. KiCad 10.0.5 also refuses footprint reference/value edits over IPC (native_field_update_unsupported), so shrinking and moving references needs an offline edit of the saved board (close clean editor, edit, reopen). Built tools/silk_place.py (candidate search with dry runs); 19 labels placed, 7 references unresolved. The skill should state the verb shapes, the minimum-height rule and the offline path for fields. | skill + bridge |-| 33 | Finish after adopt-board of a routed board | `adopt-board` clears the gate/land-route/land-pours/measure outcomes, and `route` on the adopted board re-plans every trace from scratch (it ignores existing copper), so the only way to satisfy `finish` without landing duplicate copper was an explicit empty plan documenting that nothing remains to route. aiflow should (a) route only the unconnected items of an adopted board, and (b) let the gate/land stages accept "adopted, fully routed" as a state. | bug (PR) |--## Fixed in adom-aiflow 0.1.33 (published 2026-09-29, source 64820bb, pushed directly per John)--| row | fix |-|---|---|-| 22 | run_drc takes only a kicad-cli with `pcb drc --refill-zones`; the error names `adom-aiflow-kicad-cli-remote` (now installed with the package) |-| gate phantom errors | with a native kicad-cli the gate refills zones natively and skips the raster fill (242 phantom errors became 0 on this board) |-| 33 (analyses half) | analyze current/thermal merge the board's own tracks and vias into the plan, so an adopted routed board is analysed on its real copper; `route` still re-plans every trace (open) |-| 24 | Kelvin tap keepouts numbered per net |-| 27 | tap keepouts on the segment's own layer, both layers only at its vias, and stopped short of the power pin |-| 28 | thermal vias for small pins go 0.6/0.3 just outside the pad, clear of other nets, stitch vias and board vias; `pour` says how many fit |-| fab naming | the live docs, skills, flows and run logs now name the fab "3rd party fab" (0.1.36) |--Still open: 23 (land route resume), 25 (router layer policy), 26 (pack rotations for chains), 29 (via net enforcement, clip manifest), 30 (clips sub-readme in the binary), 31 (tour fields on a localhost proxy), 32 (silk text contract), 33 (route only the unconnected items).--## Fixed in adom-aiflow 0.1.34 and 0.1.35 (2026-09-29)--| row | fix |-|---|---|-| 2 to 20, 25, 26, 30, 32 | 0.1.34: nine companion skills (intake, sourcing, circuit design, simulate, schematic to board, molecule, power layout, credentials, live clips) and a companion-skills table in the main skill; the gate/binary halves stay open |-| 29 (clip manifest) | 0.1.35: `recut` and `compose` recover clip files from the ledger by recording id (5 of 14 came back here); the via net enforcement half stays open |-| 34 (new) | `compose` wrote run-relative paths into ffmpeg concat lists, so a relative `--run` could never assemble the video; 0.1.35 writes absolute paths |-| 35 (new, open) | a clip stop records `./run/<clip>.mp4` as the local file even when the pull from the desktop failed: 4 of 14 clips (components, current, silkscreen, routing 2) never reached the container and nothing said so. The stop should check the file landed, retry the pull, and flag the capture `pullFailed` with the remote path so `recut` can fetch it later. By the time the pull was retried the desktop's recordings folder had been cleaned, so these four clips are gone for good: the pull has to be verified before the stop returns, not later |--## Closed in adom-aiflow 0.1.37 (2026-09-30)--Every remaining row is closed in the binary; see docs/release-0.1.37.md on adom/adom-aiflow.--| row | closed by |-|---|---|-| 1 | `intake --prompt-time`: the run and its clock start before any board; `start --board` attaches it later |-| 3, 4, 5 | `sourcing check --bom`: board references vs BOM, profile rules (`fab` or `jlcpcb`), dated stock, thin stock; finish requires it |-| 6, 7, 12 | `evidence add --kind calcs|simulation|vendor-model`; finish requires `requireEvidence`; vendor models run in adom/adom-spice-skillpack |-| 8 | `netlist check` (58/58 pins on this board); `start --sch` makes finish require it |-| 9 | `molecule check` (clean on this board) |-| 10 | `fab.rules` + `rules install --profile jlcpcb`; the 3rd party fab's rules stay private |-| 16, 17, 32 | bridge bugs, filed: adom/pup-bridge#127, adom/adom-bridge#220, comment on adom/kicad-bridge#104 |-| 20 | `models` checks each model's orientation and seating |-| 23 | `land route` skips what already landed, retries one trace after a lost reply, `--from` |-| 25 | `planeUnder` in the router and the gate |-| 26 | `chains` in `place pack`, plus pad-adjacency scoring |-| 29 | vias checked against other nets before landing and read back after |-| 30 | `clips --page --push`, and automatic on every clip stop once a page is set |-| 31 | `tour fields` films a localhost Fields URL on the user's own machine |-| 33 | `route` on a board with copper plans only what is unconnected; empty plans pass gate, land and finish |-| 35 | clip pulls are verified and retried; `pullFailed` clips are pulled again by recut, finish and deliver |--**New finding from the new gate:** with `planeUnder` scoped to the input hot loop (C2, C3, C4, U1 VIN and GND pads, 0.5 mm margin), this board fails: an EN via at (111.90, 91.00) and about 1.2 mm of EN track, plus about 5.3 mm of the VOUT sense trace, sit on B.Cu under the loop. The old flow let it through. Fixing it is a reroute of EN and the VOUT sense on the live board.--## Found in the rework and silkscreen pass (2026-09-30)--| # | gap | fix belongs in |-|---|---|---|-| 36 (fixed in 0.1.38) | `capture start` after the editor was closed and reopened used the run's stored window handle (724124), which no longer existed, so the recorder did not start and the first 23 label groups went on unfilmed. It should rediscover the editor window (by board path) when the stored one is gone. | aiflow (capture) |-| 37 (documented in 0.1.38) | `kicad_silk_text_batch` takes rotation as `rotation` (it refuses `angle` with "unsupported text field angle"), and it caps the stroke at a quarter of the text height, so on a board whose minimum stroke is 0.08 mm, 0.30 mm text is impossible (0.32 mm is the floor). Neither is in the verb's documentation. | kicad-bridge docs, aiflow-silkscreen skill |-| 38 (fixed in 0.1.38) | the silkscreen clip was 2.7 GB for 17 minutes (about 2.6 MB/s); the bridge pull failed after 10 minutes and ConfRoomROG has no ffmpeg to shrink it. It came across split into 200 MB parts with PowerShell. The recorder's bitrate, or a transcode before the pull, should keep a step clip pullable. | adom-bridge recorder, aiflow (pull in parts) |-| 39 | the silkscreen dashboard replay recording opens in a Hydrogen webview on the user's machine; with the test box rule ("use the test box so the user is not disturbed") it was not recorded. The dashboard's board.json and events.jsonl are in the run for a later replay. | aiflow-silkscreen (a test-box surface for the dashboard) |-| 40 (fixed in 0.1.39) | the ICs' 3D models had no MPN mark: the components step's marking defaulted to "ask" and was skipped; and the adom-chip-laser service repaints the whole part black and grey and writes across X, so its output cannot be used directly (filed as adom/adom-chip-laser#2). 0.1.39 adds `adom-aiflow-etch` (colour-preserving, along the long axis, Y-up models stood up first), makes marking the default for ICs, and `finish` checks it. | aiflow (tool, default, gate), adom-chip-laser |-| 41 (skills fixed in 0.1.39) | the three component pages made here (through molecule-publish's "create missing component pages" stage) had plain thumbnails as heroes, not the eda-component-hero art (etched part, copper outlines, silkscreen, pin labels); aiflow-sourcing and aiflow-molecule now require it whenever a component page is made | aiflow skills |-| 42 (fixed in 0.1.40) | the rework run's `report --push` rebuilt docs/clips.md from its own clips and overwrote the first run's clips page; the first run now owns docs/clips.md and later runs publish docs/clips-<run>.md with a link | aiflow (clips) |-| 43 (fixed in 0.1.41 and 0.1.42) | the etch mark was 3D text (an extruded solid per glyph: 1,760 triangles on a 920-triangle SOT-23-6); it is now flat, each glyph's top face only (359 triangles, same look), and its colour is stored in the STEP (a located transform had made the writer drop it) | aiflow (etch tool) |-| 44 (0.1.41) | the etch tool installed OpenCascade locally (about 1.3 GB) on first use, against the rule that STEP geometry work happens on the shared services; it now refuses unless the user agrees (`AIFLOW_ALLOW_LOCAL_OCC=1`), until adom-chip-laser keeps colours, turns the part and writes flat marks itself (adom/adom-chip-laser#2, flat mark added in a comment) | aiflow, adom-chip-laser |-| 45 (0.1.43) | the local OpenCascade the etch tool needs was the full `cadquery-ocp` (1.3 GB, mostly the VTK viewer it never uses); it now installs `cadquery-ocp-novtk` (0.4 GB), and aiflow-sourcing suggests that build for any local STEP work | aiflow (etch tool, sourcing skill) |-| 46 (fixed in 0.1.44) | the etch service lays its mark at the part's bounding-box top, so on MLCCs and chip resistors (ceramic 20 to 45 µm below the end caps) the text floated above the body; the tool now seats it on the surface under the text. The first C2/C3 etch was also dark on a dark-brown body, and C2/C3 still pointed at KiCad's stock 1206 model, so the etched STEP never reached the board | aiflow (etch tool, board flow) |-| 47 (fixed in 0.1.44) | on C1 (electrolytic) the long-axis rule ran the text across the black polarity stripe; `--along x|y` turns it onto the silver field. L1's vendor model already prints its part number and would have been etched twice; the flow now leaves vendor markings alone | aiflow (etch tool, board flow) |-| 48 (fixed in 0.1.45) | LEDs had no MPN mark, and a top mark would cover the window; `--face side` puts it on a long side face (`--side-band low` when a see-through window runs the full length, like the WS2812B-2020). LED models now carry their lens colour from the datasheet's dominant wavelength, softened, as the default STEP on the Adom basic-part pages | aiflow (etch tool), adom-basic-parts |-| 49 | the KiCad 3D viewer on the desktop can't be filmed while another window covers it (the window capture is blank for the GL canvas), so the etch clip is built from `kicad-cli pcb render` before/after frames | adom-bridge recorder, aiflow-live-clips |-| 50 | the component pages this board depends on had real library errors that only showed up while redoing their models: the WS2812B-2020 page carried the 5050 model and the 5050 pinout (fixed), the Inolux LED STEPs are KiCad's generic models and taller than the parts, and the 0402 LED pages' `.adom-lbr.json` pads differ from their `.kicad_mod` | component pages (Adom basic parts) |