12 V to 5 V / 1 A Buck Molecule (TPS54202)

@@ -1,6 +1,6 @@ # Board: molecule format, placement, routing, pours -![Final board in KiCad's native 3D viewer: contacts labelled VIN, GND, EN on the left and VOUT, GND, VMON on the right, four corner machine pins](docs/img/board-3d.png)+![Final board, KiCad 10 3D render: contacts labelled VIN, GND, EN on the left and VOUT, GND, VMON on the right, four corner machine pins](docs/img/board-3d.png)  ## Molecule format @@ -26,7 +26,7 @@ This buck is an Adom molecule: a small board with machine pins and contacts on a | J6 | (24, 4) | VMON | VOUT / 2, for a 3.3 V ADC | | MP1 to MP4 | (0, 0), (24, 0), (0, 16), (24, 16) | GND | mechanical and ground | -Everything that connects to the molecule depends on these ten positions. The adom-aiflow spec lists them as fixed parts, so placement never moves them.+Everything that connects to the molecule depends on these ten positions, so they are fixed parts in the layout spec (`aiflow/spec.json`).  ## Design rules @@ -47,60 +47,45 @@ Two Kelvin connections come from datasheet 7.4.1. The divider's ground (R3.2) re  ## Placement -adom-aiflow started with 10 interface parts fixed and 20 parts parked outside the outline. The AI placed the parts: it wrote the intended spots in `aiflow/wishes.json` and used `place pack` to find legal spots and `place check` to run DRC on the moved board. `place land` then put 24 parts on the board live in KiCad, one at a time, each as its own undo step, in 21.1 s.--The placement follows the power path:+The ten interface parts (four machine pins and six contacts) are fixed by the molecule grid. The other parts were placed around the power path, with every placement checked against KiCad's DRC before it was committed:  - the input hot loop (C2, C3, C4 to U1 VIN, to U1 GND, and back to the capacitor grounds) is tight on F.Cu next to U1; - L1 is to the right of U1, with the output capacitors around it; - the feedback chain R1, R2, C9, R3 is a column left of U1, away from SW; - the EN divider sits beside J3. -## Routing and the rework--The grid router closed every connection in 5 passes: 48 traces, 313 segments, 24 vias, 253 mm of copper. The offline gate passed with 0 new DRC errors and 0 unconnected. During the live landing, the KiCad bridge dropped one reply at trace 35 of 48. `land route` cannot resume, so we checked the live revision to confirm trace 35 had not landed, then landed the remaining 14 traces from a hand-built resume plan.--![Board after the router, before the rework: VOUT and FB copper on B.Cu under the hot loop](docs/img/board-before-rework.png)--**What went wrong.** The router treated B.Cu as free space. It put 17.5 mm of VOUT and 2.8 mm of FB on the bottom layer under the hot loop (U1 and the input capacitors). The VOUT Kelvin sense ran 10 mm on B.Cu under the input capacitors, cutting the ground plane right where the hot loop needs it. Nothing in the spec could say "B.Cu is the ground plane here". The Fields solve and a review of the live copper both flagged it.--**The rework, done by hand live through the KiCad bridge.** Each route was dry-run first and committed only at 0 DRC errors, each as its own undo step.--1. Removed FB, the LED net and the VOUT copper under the hot loop (79 items), then FB and FBM (16 items).-2. Moved R6 and D1 beside the output cluster. Turned R1, R2 and C9 by 180 deg, so the chain reads VOUT, R1, FBM, R2, FB from top to bottom. The packer had picked each part's rotation independently, which knotted the chain and put a router via inside an 0402 pad. After the turn, FBM is a straight 1 mm link.-3. Routed FBM straight, the FB spine, and a 0.15 mm FB jog to R3 (between R3's GND via and U1's EN pad). The VOUT Kelvin sense now runs along the top edge on B.Cu to C6.1, away from the hot loop.-4. Validated the live board: 0 errors, 0 unconnected.+## Routing -After the rework the board has 250 track segments and 19 vias, down from 313 and 24.+The first routing pass closed every connection: 48 traces, 24 vias, 253 mm of copper, 0 DRC errors and 0 unconnected. +![Board after the first routing pass, before the rework: VOUT and FB copper on B.Cu under the hot loop](docs/img/board-before-rework.png) -### Second rework (2026-09-30): the ground plane under the input loop+That first pass treated B.Cu as free space. It put 17.5 mm of VOUT and 2.8 mm of FB on the bottom layer under the hot loop (U1 and the input capacitors), and the VOUT Kelvin sense ran 10 mm on B.Cu under the input capacitors, cutting the ground plane right where the hot loop returns. Two reworks fixed it. Each route was checked against KiCad's DRC before it was committed. -adom-aiflow 0.1.37 added a `planeUnder` gate: B.Cu under the input hot loop (C2, C3, C4 to U1's VIN and GND pins) belongs to GND. It failed this board. An EN via at (111.90, 91.00) and its bottom-layer track, plus about 5 mm of the VOUT sense trace, ran on B.Cu under the loop, and the first flow had let them through.+1. FB, the LED net and the VOUT copper under the hot loop were removed and routed again.+2. R6 and D1 moved beside the output cluster. R1, R2 and C9 were turned 180 deg, so the chain reads VOUT, R1, FBM, R2, FB from top to bottom and FBM is a straight 1 mm link.+3. FB runs as a spine with a 0.15 mm jog to R3 (between R3's GND via and U1's EN pad).+4. EN drops to B.Cu at (110.9, 89.2), left of U1 and outside the hot loop. The VOUT sense runs along the top edge on F.Cu and changes layer at x 110.2 and x 117.2, both outside the loop. -In a measured rework run, EN and the VOUT sense path were removed as one undo step and routed again by aiflow's router, which keeps other nets out of the region. EN now drops to B.Cu at (110.9, 89.2), left of U1 and outside the loop. The VOUT sense runs along the top edge on F.Cu and changes layer at x 110.2 and x 117.2, both outside the region.--The same ten zones were landed again and filled natively. The gate passes: 0 new DRC errors, 0 unconnected, region clear. The Fields solve is unchanged: SW peak 50 A/mm2, still-air rise +50 C, 0 issues. Copper is B.Cu 498.8 mm2 and F.Cu 434.9 mm2 (it was 492.8 and 448.8).+The result: B.Cu under the input hot loop (C2, C3, C4 to U1's VIN and GND pins) carries nothing but GND, and the board passes DRC with 0 errors and 0 unconnected.  ## Pours -The first pour plan had 22 zones, 19 of them Kelvin keepouts. Its first landing was refused because the keepouts had duplicate names; they were renumbered and landed. The Fields solve on that board found two problems:+The pours were shaped by the [current and thermal analysis](thermal-current.md). Two findings on the first pour set drove the changes: -- **SW neck at 215 A/mm2 at U1.2.** SW was a trace only (a deliberate choice to keep the switching node small), and the trace necked down at the pin.-- **U1 at +51 C in still air.** The Kelvin keepouts were drawn on both layers right up to the power pin. They fenced U1's GND pin off from the ground pour, which is its main heat path, and there were no thermal vias.+- **SW neck at 215 A/mm2 at U1.2.** SW was a trace only (to keep the switching node small), and the trace necked down at the pin.+- **U1 at +51 C in still air.** Kelvin keepouts drawn on both layers right up to the power pins fenced U1's GND pin off from the ground pour, which is its main heat path, and there were no thermal vias. -Pour revision 2 fixed both:+The final pours: -- a small **solid SW patch** from U1.2 to L1.1, widening toward the inductor, so the switching node gains copper only where the current flows;+- a small **solid SW patch** from U1.2 to L1.1, opening right after U1.2 (x = 113.85) and widening toward the inductor, so the switching node gains copper only where the current flows; - **solid connections** (no thermal relief) at U1.1, U1.3, L1.1 and L1.2; - Kelvin keepouts only at the two sense pads (R3.2, R1.1);-- **three GND vias** (0.6 / 0.3 mm) in solid GND copper: two under U1.1 at (113.3, 92.55) and (113.9, 92.75), and one beside C4.2 at (115.55, 88.45). The planner's own thermal via landed inside the SOT-23 pad (a 0.8 mm via-in-pad that would wick solder), so these were placed by hand.--Two "GND" vias from the plan had landed touching the router's SW trace, and KiCad gave them the SW net. They were removed, along with two GND vias and three GND tracks inside the SW corridor. The re-run current analysis then found a 0.95 mm throat in the SW patch at 60 A/mm2, right at the screening threshold. In revision 3 the polygon opens right after U1.2 (x = 113.85). The final peak is 50 A/mm2 (see [thermal and current](thermal-current.md)).+- **three GND vias** (0.6 / 0.3 mm) in solid GND copper: two under U1.1 at (113.3, 92.55) and (113.9, 92.75), and one beside C4.2 at (115.55, 88.45). They sit beside the SOT-23 pads, not in them, so no via wicks solder from a pad. -We also tested adding 8 more GND vias at the nearest free spots, 2.6 to 3.8 mm from U1.1. It changed U1's temperature by 0 C in the Fields solve, so they were left out.+The SW peak dropped from 215 to 50 A/mm2 (see [thermal and current](thermal-current.md)). Eight more GND vias at the nearest free spots, 2.6 to 3.8 mm from U1.1, changed U1's temperature by 0 C in the solve, so they were left out. -![The SW net selected as a whole: the solid patch from U1 pin 2 to the inductor, the bootstrap link and TP1](docs/img/sw-patch.png)+![The SW net selected as a whole in KiCad: the solid patch from U1 pin 2 to the inductor, the bootstrap link and TP1](docs/img/sw-patch.png)  The final zones (10): @@ -115,33 +100,30 @@ The final zones (10):  These nets are deliberately not poured: BOOT (dv/dt), FB and FBM (high impedance), EN, VMON and LED. -![Final copper, top layer view](docs/img/board-final-copper.png)+![Final copper, exported from KiCad 10: F.Cu on the left, B.Cu on the right (seen from the top). B.Cu is an unbroken ground plane apart from a few short links](docs/img/board-final-copper.png) -## DRC gate and copper measurement+## DRC and copper  | check | result | |---|---| | schematic ERC (KiCad 10.0.5) | 0 violations |-| offline gate (KiCad 10.0.5 DRC, zones refilled) | 0 new errors, 0 inherited, 0 unconnected |-| live board DRC | 0 errors, 0 unconnected, 34 warnings |-| warnings | 11 library footprint notices, 9 silk over copper, 4 silk overlap, 10 text height |--On the adopted board, the gate at first reported 242 DRC errors. They were phantoms of aiflow's raster zone fill; with a native kicad-cli refilling the zones the count was 0. This is fixed in adom-aiflow 0.1.33 (see [aiflow run](aiflow-run.md)).+| board DRC (KiCad 10.0.5, zones refilled) | 0 errors, 0 unconnected |+| DRC warnings | 11 library footprint notices (the project's footprints differ from the installed KiCad library copies) | -Measured copper, read back from KiCad's own fills:+Copper area, read back from KiCad's own zone fills: -| layer | filled area | coverage |-|---|---|---|-| F.Cu | 448.78 mm2 | 80.14 % |-| B.Cu | 492.84 mm2 | 88.01 % |+| layer | filled area |+|---|---|+| F.Cu | 434.9 mm2 |+| B.Cu | 498.8 mm2 |  ## Silkscreen -The silkscreen follows adom-aiflow's silkscreen guidance (aiflow-silkscreen, `docs/silkscreen-priority-pass.md`). It was redone on 2026-09-30 after the copper was final, replacing an earlier shortcut pass.+The silkscreen was placed after the copper was final, ranked by what a person holding the board needs first. -![Top face, KiCad 10's own 3D render](docs/img/silk-top.png)+![Top face, KiCad 10 3D render of the final board](docs/img/silk-top.png) -![Bottom face, KiCad 10's own 3D render, seen from below](docs/img/silk-bottom.png)+![Bottom face, KiCad 10 3D render seen from below: contact labels, input range and the board identity block](docs/img/silk-bottom.png)  **Importance pass first.** This board is powered, switched and probed through its contacts, so the ranking was: @@ -153,11 +135,8 @@ The silkscreen follows adom-aiflow's silkscreen guidance (aiflow-silkscreen, `do  **How it was placed.** -- The layout was solved from empty label occupancy with aiflow's `silkscreen-layout`, against every pad and mask opening, all 21 vias and the holes on both faces, the board edge, and each part's fitted 3D body projected into the board plane. The contacts used the contact policy (outside first, frames), and the documentation block used the sections tool.-- aiflow's independent preflight found 0 findings, and the whole-board obstacle audit found 0 missing obstacles and 0 collisions. The smallest clearances are 0.114 mm to copper and holes, and 0.214 mm to the edge.-- **Offline half.** KiCad 10 refuses footprint field edits over its API, and the text verb draws no lines. So one offline edit hid the footprints' own reference and value fields, added the 68 frame and pointer strokes, removed the earlier pass's 19 labels, and lowered the project's minimum text height to 0.3 mm (the 3rd party fab profile).-- **Live half.** The 97 labels went on live in KiCad through the bridge, one group at a time in importance order, each group dry-run through KiCad's own DRC before it was committed.-- **Readback.** All 97 are at their designed positions and layers, and all 20 rotations are kept. The gate's native KiCad 10 DRC passes with 0 new errors.+- The layout was solved against every pad and mask opening, all 21 vias and the holes on both faces, the board edge, and each part's 3D body projected into the board plane. The smallest clearances are 0.114 mm to copper and holes, and 0.214 mm to the edge.+- The 97 labels and 68 frame and pointer strokes went on live in KiCad, one group at a time in importance order, each group checked against KiCad's DRC before it was committed. The project's minimum text height is 0.3 mm, the 3rd party fab's limit.  **Sizes and compromises.** @@ -167,6 +146,4 @@ The silkscreen follows adom-aiflow's silkscreen guidance (aiflow-silkscreen, `do - The frames are broken where they would cross a pad, a contact ring or their own text. - R2 is the only label that needed a pointer. -The full label list with sizes and reasons is in `aiflow/run-rework/silk/manifest.md` in the project folder.- The board has not been fabricated or assembled yet.

@@ -1,152 +1,160 @@-<!-- aiflow-clips-run: buck-12v5v-molecule-claude-opus-5-5-20260929-0039 --> # Build clips -The rework run (the reroute and the silkscreen) has its own page: [rework clips](clips-rework.md).+Watch the board being built in KiCad 10, step by step. Each player below runs at 10x speed. The action cut under it is the same step at real speed with the idle time removed. The clips show the board as it was at each step; the final board is on the [board page](board.md).++| # | step |+|---|---|+| 1 | [Placement](#clip-1) |+| 2 | [First routing and pours](#clip-2) |+| 3 | [Routing rework](#clip-3) |+| 4 | [Pours rework](#clip-4) |+| 5 | [SW patch widened](#clip-5) |+| 6 | [Net walkthrough](#clip-6) |+| 7 | [Adom Fields walkthrough](#clip-7) |+| 8 | [Ground plane under the input loop](#clip-8) |+| 9 | [Pours, final](#clip-9) |+| 10 | [Current analysis, final](#clip-10) |+| 11 | [Silkscreen, first groups](#clip-11) |+| 12 | [Silkscreen](#clip-12) |+| 13 | [3D walkthrough](#clip-13) |+| 14 | [Part models: laser etch and LED colour](#clip-14) |++## 1. Placement -Every step of the adom-aiflow run records its own clip of the KiCad window on the test box. This page is appended as each clip lands, so it can stay open in a browser tab while the build runs.--Last updated 2026-09-29 17:04 UTC. 9 clip(s).+<a id="clip-1"></a> -| # | step | recorded | clip | state |-|---|---|---|---|---|-| 1 | 3D walkthrough (KiCad 3D viewer) | 2026-09-29 14:13 UTC | [10x cut](#clip-1) | ok |-| 2 | Placement (and the first traces) | 2026-09-29 02:34 UTC | [10x cut](#clip-2) | ok |-| 3 | Routing landed, first pours | 2026-09-29 02:57 UTC | [10x cut](#clip-3) | see note |-| 4 | Fields walkthrough (Adom Fields app) | 2026-09-29 12:52 UTC | [10x cut](#clip-4) | ok |-| 5 | Routing rework (back from the current analysis) | 2026-09-29 11:56 UTC | [10x cut](#clip-5) | ok |-| 6 | Pours rework (back from the Fields solve) | 2026-09-29 12:11 UTC | [10x cut](#clip-6) | ok |-| 7 | Thermal analysis, SW throat widened | 2026-09-29 12:43 UTC | [10x cut](#clip-7) | ok |-| 8 | Net walkthrough (GND, SW, VIN, VOUT) | 2026-09-29 12:57 UTC | [10x cut](#clip-8) | ok |-| 9 | Silkscreen | 2026-09-29 14:12 UTC | [10x cut](#clip-9) | see note |+The parts parked below the outline land on the molecule one at a time, each its own KiCad undo step, starting with the input hot loop around U1. The first traces appear at the end. -### Clip 1: 3D walkthrough (KiCad 3D viewer)+<video src="docs/clips/window-461694-20260929-023413-10x.mp4" poster="docs/clips/window-461694-20260929-023413-poster.jpg" controls muted playsinline preload="metadata"></video> -<a id="clip-1"></a>+[Watch the action cut (idle time removed, real speed)](https://wiki.adom.inc/api/pages/john/buck-12v5v-molecule/files/docs/clips/window-461694-20260929-023413-action.mp4) -Recorded 2026-09-29 14:13 UTC. 31 View-menu commands, no mouse: the bottom identity silkscreen, tilted and close views with the contact and probe labels, the side view with the medium machine pins under the board, and the top view.+## 2. First routing and pours -<video src="docs/clips/window-3933648-20260929-141309-10x.mp4" poster="docs/clips/window-3933648-20260929-141309-poster.jpg" controls muted playsinline preload="metadata"></video>+<a id="clip-2"></a> -Motion-only action cut: [docs/clips/window-3933648-20260929-141309-action.mp4](clips/window-3933648-20260929-141309-action.mp4)+The 48 routed traces on the board, then the first pours filling: GND on both layers, VIN and VOUT on top. -Contact sheet (nine frames): ![clip 1 contact sheet](docs/clips/window-3933648-20260929-141309-sheet.png)+<video src="docs/clips/window-461694-20260929-025743-10x.mp4" poster="docs/clips/window-461694-20260929-025743-poster.jpg" controls muted playsinline preload="metadata"></video> -Raw recording: `window-3933648-20260929-141309.mp4`, 52 MB, kept with the run (not uploaded).+[Watch the action cut (idle time removed, real speed)](https://wiki.adom.inc/api/pages/john/buck-12v5v-molecule/files/docs/clips/window-461694-20260929-025743-action.mp4) -### Clip 2: Placement (and the first traces)+## 3. Routing rework -<a id="clip-2"></a>+<a id="clip-3"></a> -Recorded 2026-09-29 02:34 UTC. The 24 parts parked in a row below the outline land on the molecule one at a time, each its own KiCad undo step; the first traces appear at the end.+FB and VOUT come off the bottom layer under the input hot loop. The feedback column (R1, R2, C9) is turned 180 degrees so it reads VOUT, R1, FBM, R2, FB, the LED moves beside the output, and the VOUT sense is routed along the top edge. -<video src="docs/clips/window-461694-20260929-023413-10x.mp4" poster="docs/clips/window-461694-20260929-023413-poster-v2.jpg" controls muted playsinline preload="metadata"></video>+<video src="docs/clips/window-593052-20260929-115650-10x.mp4" poster="docs/clips/window-593052-20260929-115650-poster.jpg" controls muted playsinline preload="metadata"></video> -Motion-only action cut: [docs/clips/window-461694-20260929-023413-action.mp4](clips/window-461694-20260929-023413-action.mp4)+[Watch the action cut (idle time removed, real speed)](https://wiki.adom.inc/api/pages/john/buck-12v5v-molecule/files/docs/clips/window-593052-20260929-115650-action.mp4) -Contact sheet (nine frames): ![clip 2 contact sheet](docs/clips/window-461694-20260929-023413-sheet.png)+## 4. Pours rework -Raw recording: `window-461694-20260929-023413.mp4`, 984 MB, kept with the run (not uploaded).+<a id="clip-4"></a> -### Clip 3: Routing landed, first pours+The SW patch from U1 to the inductor, solid ground at U1's GND pin with thermal vias, and every zone refilled. -<a id="clip-3"></a>+<video src="docs/clips/window-593052-20260929-121139-10x.mp4" poster="docs/clips/window-593052-20260929-121139-poster.jpg" controls muted playsinline preload="metadata"></video> -Recorded 2026-09-29 02:57 UTC. The 48 routed traces on the board, then the first pours filling (GND on both layers, VIN and VOUT on top).+[Watch the action cut (idle time removed, real speed)](https://wiki.adom.inc/api/pages/john/buck-12v5v-molecule/files/docs/clips/window-593052-20260929-121139-action.mp4) -> Note: aiflow flagged it blank; that is a false positive: the check samples the middle of the window and the board sits left of centre at this zoom (the sheet shows real footage).+## 5. SW patch widened -<video src="docs/clips/window-461694-20260929-025743-10x.mp4" poster="docs/clips/window-461694-20260929-025743-poster-v2.jpg" controls muted playsinline preload="metadata"></video>+<a id="clip-5"></a> -Motion-only action cut: [docs/clips/window-461694-20260929-025743-action.mp4](clips/window-461694-20260929-025743-action.mp4)+The SW patch opens right after U1's SW pin and the pours are filled again. Over the rework the SW peak current density falls from 215 to 50 A/mm2. -Contact sheet (nine frames): ![clip 3 contact sheet](docs/clips/window-461694-20260929-025743-sheet.png)+<video src="docs/clips/window-593052-20260929-124348-10x.mp4" poster="docs/clips/window-593052-20260929-124348-poster.jpg" controls muted playsinline preload="metadata"></video> -Raw recording: `window-461694-20260929-025743.mp4`, 1110 MB, kept with the run (not uploaded).+[Watch the action cut (idle time removed, real speed)](https://wiki.adom.inc/api/pages/john/buck-12v5v-molecule/files/docs/clips/window-593052-20260929-124348-action.mp4) -### Clip 4: Fields walkthrough (Adom Fields app)+## 6. Net walkthrough -<a id="clip-4"></a>+<a id="clip-6"></a> -Recorded 2026-09-29 12:52 UTC. The Fields app walks the solved board: heat flow in each copper layer in 3D with the vias, the bottom ground plane, temperature in still air (+44 C at U1) and moving air (+24 C), and current density. 0 issues against the 55 C budget.+Each key net selected as a whole in KiCad (pours, tracks, vias and pads together): GND, the SW patch from U1 to the inductor, VIN and VOUT. -<video src="docs/clips/window-4852048-20260929-125229-10x.mp4" poster="docs/clips/window-4852048-20260929-125229-poster-v2.jpg" controls muted playsinline preload="metadata"></video>+<video src="docs/clips/window-593052-20260929-125701-10x.mp4" poster="docs/clips/window-593052-20260929-125701-poster.jpg" controls muted playsinline preload="metadata"></video> -Motion-only action cut: [docs/clips/window-4852048-20260929-125229-action.mp4](clips/window-4852048-20260929-125229-action.mp4)+[Watch the action cut (idle time removed, real speed)](https://wiki.adom.inc/api/pages/john/buck-12v5v-molecule/files/docs/clips/window-593052-20260929-125701-action.mp4) -Contact sheet (nine frames): ![clip 4 contact sheet](docs/clips/window-4852048-20260929-125229-sheet.png)+## 7. Adom Fields walkthrough -Raw recording: `window-4852048-20260929-125229.mp4`, 181 MB, kept with the run (not uploaded).+<a id="clip-7"></a> -### Clip 5: Routing rework (back from the current analysis)+The Adom Fields app on the solved board: heat flow in each copper layer in 3D with the vias, the bottom ground plane, temperature in still and moving air, and current density. -<a id="clip-5"></a>+<video src="docs/clips/window-4852048-20260929-125229-10x.mp4" poster="docs/clips/window-4852048-20260929-125229-poster.jpg" controls muted playsinline preload="metadata"></video> -Recorded 2026-09-29 11:56 UTC. FB and VOUT come off the bottom layer under the input hot loop; the feedback column (R1, R2, C9) is turned 180 degrees so it reads VOUT, R1, FBM, R2, FB; the LED moves beside the output; the VOUT sense re-routes along the top edge.+[Watch the action cut (idle time removed, real speed)](https://wiki.adom.inc/api/pages/john/buck-12v5v-molecule/files/docs/clips/window-4852048-20260929-125229-action.mp4) -<video src="docs/clips/window-593052-20260929-115650-10x.mp4" poster="docs/clips/window-593052-20260929-115650-poster.jpg" controls muted playsinline preload="metadata"></video>+## 8. Ground plane under the input loop -Motion-only action cut: [docs/clips/window-593052-20260929-115650-action.mp4](clips/window-593052-20260929-115650-action.mp4)+<a id="clip-8"></a> -Contact sheet (nine frames): ![clip 5 contact sheet](docs/clips/window-593052-20260929-115650-sheet.png)+EN and the VOUT sense come off B.Cu under the input hot loop and are routed again outside it, so B.Cu under the loop carries only GND. -Raw recording: `window-593052-20260929-115650.mp4`, 463 MB, kept with the run (not uploaded).+<video src="docs/clips/window-724124-20260930-013402-10x.mp4" poster="docs/clips/window-724124-20260930-013402-poster.jpg" controls muted playsinline preload="metadata"></video> -### Clip 6: Pours rework (back from the Fields solve)+[Watch the action cut (idle time removed, real speed)](https://wiki.adom.inc/api/pages/john/buck-12v5v-molecule/files/docs/clips/window-724124-20260930-013402-action.mp4) -<a id="clip-6"></a>+## 9. Pours, final -Recorded 2026-09-29 12:11 UTC. SW patch from U1 to the inductor, solid ground at U1's GND pin with thermal vias, the stray SW vias and corridor GND vias removed, every zone refilled.+<a id="clip-9"></a> -<video src="docs/clips/window-593052-20260929-121139-10x.mp4" poster="docs/clips/window-593052-20260929-121139-poster.jpg" controls muted playsinline preload="metadata"></video>+The ten zones landed again and filled natively in KiCad. -Motion-only action cut: [docs/clips/window-593052-20260929-121139-action.mp4](clips/window-593052-20260929-121139-action.mp4)+<video src="docs/clips/window-724124-20260930-014523-10x.mp4" poster="docs/clips/window-724124-20260930-014523-poster.jpg" controls muted playsinline preload="metadata"></video> -Contact sheet (nine frames): ![clip 6 contact sheet](docs/clips/window-593052-20260929-121139-sheet.png)+[Watch the action cut (idle time removed, real speed)](https://wiki.adom.inc/api/pages/john/buck-12v5v-molecule/files/docs/clips/window-724124-20260930-014523-action.mp4) -Raw recording: `window-593052-20260929-121139.mp4`, 87 MB, kept with the run (not uploaded).+## 10. Current analysis, final -### Clip 7: Thermal analysis, SW throat widened+<a id="clip-10"></a> -<a id="clip-7"></a>+The board while the current and thermal checks run on the final copper: SW peak 50 A/mm2, 0 issues. -Recorded 2026-09-29 12:43 UTC. The board while the current and thermal gates ran; the SW patch opened right after U1's SW pin and the pours were re-landed (peak current density 215 to 50 A/mm2 over the rework).+<video src="docs/clips/window-724124-20260930-015230-10x.mp4" poster="docs/clips/window-724124-20260930-015230-poster.jpg" controls muted playsinline preload="metadata"></video> -<video src="docs/clips/window-593052-20260929-124348-10x.mp4" poster="docs/clips/window-593052-20260929-124348-poster.jpg" controls muted playsinline preload="metadata"></video>+[Watch the action cut (idle time removed, real speed)](https://wiki.adom.inc/api/pages/john/buck-12v5v-molecule/files/docs/clips/window-724124-20260930-015230-action.mp4) -Motion-only action cut: [docs/clips/window-593052-20260929-124348-action.mp4](clips/window-593052-20260929-124348-action.mp4)+## 11. Silkscreen, first groups -Contact sheet (nine frames): ![clip 7 contact sheet](docs/clips/window-593052-20260929-124348-sheet.png)+<a id="clip-11"></a> -Raw recording: `window-593052-20260929-124348.mp4`, 344 MB, kept with the run (not uploaded).+The first label groups going on. -### Clip 8: Net walkthrough (GND, SW, VIN, VOUT)+<video src="docs/clips/window-724124-20260930-031802-10x.mp4" poster="docs/clips/window-724124-20260930-031802-poster.jpg" controls muted playsinline preload="metadata"></video> -<a id="clip-8"></a>+[Watch the action cut (idle time removed, real speed)](https://wiki.adom.inc/api/pages/john/buck-12v5v-molecule/files/docs/clips/window-724124-20260930-031802-action.mp4) -Recorded 2026-09-29 12:57 UTC. Each key net selected as a whole in KiCad (pours, tracks, vias and pads together) and framed with Zoom to Selection: GND (137 items), the SW patch from U1 to the inductor (33), VIN (40), VOUT (56).+## 12. Silkscreen -<video src="docs/clips/window-593052-20260929-125701-10x.mp4" poster="docs/clips/window-593052-20260929-125701-poster.jpg" controls muted playsinline preload="metadata"></video>+<a id="clip-12"></a> -Motion-only action cut: [docs/clips/window-593052-20260929-125701-action.mp4](clips/window-593052-20260929-125701-action.mp4)+The two-sided silkscreen placed live, one label group at a time in importance order: contact functions in frames on both faces, probe pads, every reference with its value, and the board identity block on the bottom. Each group is checked against KiCad's DRC before it is committed. -Contact sheet (nine frames): ![clip 8 contact sheet](docs/clips/window-593052-20260929-125701-sheet.png)+<video src="docs/clips/window-527520-20260930-033042-10x.mp4" poster="docs/clips/window-527520-20260930-033042-poster.jpg" controls muted playsinline preload="metadata"></video> -Raw recording: `window-593052-20260929-125701.mp4`, 189 MB, kept with the run (not uploaded).+[Watch the action cut (idle time removed, real speed)](https://wiki.adom.inc/api/pages/john/buck-12v5v-molecule/files/docs/clips/window-527520-20260930-033042-action.mp4) -### Clip 9: Silkscreen+## 13. 3D walkthrough -<a id="clip-9"></a>+<a id="clip-13"></a> -Recorded 2026-09-29 14:12 UTC. Contact functions landing on both faces beside every machine contact (VIN, GND, EN, VOUT, GND, VMON), probe-pad labels (SW, FB, VOUT, GND) and the bottom identity block, each label dry-run against KiCad's DRC before it landed.+The finished board in KiCad's 3D viewer: top, tilted and close views, the side view with the machine pins, and the bottom. -> Note: stopped by aiflow's clip guard after 43 min (budget 10 min); no 10x cut or contact sheet was made, the raw recording is kept with the run+<video src="docs/clips/window-18616902-20260930-104837-10x.mp4" poster="docs/clips/window-18616902-20260930-104837-poster.jpg" controls muted playsinline preload="metadata"></video> -<video src="docs/clips/window-724124-20260929-141234-10x.mp4" poster="docs/clips/window-724124-20260929-141234-poster.jpg" controls muted playsinline preload="metadata"></video>+[Watch the action cut (idle time removed, real speed)](https://wiki.adom.inc/api/pages/john/buck-12v5v-molecule/files/docs/clips/window-18616902-20260930-104837-action.mp4) -Motion-only action cut: [docs/clips/window-724124-20260929-141234-action.mp4](clips/window-724124-20260929-141234-action.mp4)+## 14. Part models: laser etch and LED colour -Contact sheet (nine frames): ![clip 9 contact sheet](docs/clips/window-724124-20260929-141234-sheet.png)+<a id="clip-14"></a> -Raw recording: `window-724124-20260929-141234.mp4`, 59 MB, kept with the run (not uploaded).+Every marked part carries its MPN as a flat laser-etch mark on its 3D model, with the vendor colours kept: U1 along its long axis, C1 on the silver field of the can (off the polarity stripe), C2 and C3 on the ceramic between the end caps, and every 0402 and 0603 part the same way. D1's lens is tinted to the datasheet's 527 nm dominant wavelength, with its MPN on the side of the lens so the window stays clear. L1's vendor model already carries its AMPLH5030S marking. Each view is a KiCad 10 render of the same board, before and after. +<video src="docs/clips/etch-cleanup.mp4" poster="docs/clips/etch-cleanup-poster.jpg" controls muted playsinline preload="metadata"></video> +[Open the clip on its own](https://wiki.adom.inc/api/pages/john/buck-12v5v-molecule/files/docs/clips/etch-cleanup.mp4)

@@ -1,13 +1,13 @@ # Current density and thermal: Adom Fields on the real copper -The board's copper was solved with Adom Fields, run from adom-aiflow (`adom-fields analyze`). Fields builds a copper map from the board's filled pours, tracks, pads and vias on a 0.2 mm grid (140 x 100 cells) and computes two things:+The board's copper was solved with Adom Fields. Fields builds a copper map from the board's filled pours, tracks, pads and vias on a 0.2 mm grid (140 x 100 cells) and computes two things:  - **current**: a DC conduction solve for each loaded net, between its terminals; - **heat**: a steady-state solve with the layers coupled through the dielectric and every via barrel, losing heat to the air on both faces.  It is a screening model. It covers the rectangular outline, the chip powers from the spec and convection only; there is no radiation, no airflow solve and no junction-temperature qualification. The results guided the layout. None of this has been measured on hardware; the board has not been built yet. -![The Adom Fields app on the final board: current density on F.Cu, SW peak 50 A/mm2, 0 issues](docs/img/fields-app.png)+![The Adom Fields app on the final board: current density on F.Cu with the parts shown see-through, SW peak 50 A/mm2, U1 +45 C and L1 +41 C, 0 issues](docs/img/fields-app.png)  ## Inputs from the spec @@ -26,82 +26,69 @@ It is a screening model. It covers the rectangular outline, the chip powers from | board state | SW peak | what changed | |---|---|---| | first pours (SW as a trace only) | **215 A/mm2** at U1.2 | the trace necked down at U1's SW pin |-| SW patch added (pours revision 2), SW corridor cleaned | **60 A/mm2**, at a 0.95 mm throat next to U1.2 | the patch still had a throat right at the pin; 60 A/mm2 is the screening threshold, so `analyze current` refused it |-| patch polygon opened right after U1.2 (revision 3) | **50 A/mm2** | final |+| SW patch added | **60 A/mm2**, at a 0.95 mm throat next to U1.2 | the patch still had a throat right at the pin, at the 60 A/mm2 screening threshold |+| patch polygon opened right after U1.2 (final) | **50 A/mm2** | |  The response to the 215 A/mm2 reading was a small solid SW patch, not an SW pour. The patch adds copper only between U1.2 and L1.1, where the current flows, and the switching node's area (and its radiated field) stays small. [Board](board.md) has the full story. -![Current density on both copper layers after the rework: SW peak 50 A/mm2 on F.Cu, the B.Cu ground plane quiet](docs/img/current-density.png)+![Current density in the SW net on F.Cu, from the top: the current spreads from U1 pin 2 through the solid patch into L1, peak 50 A/mm2 at the pin](docs/img/current-density.png)  Final Fields peaks per net: -| net | load | peak current density | where |-|---|---|---|---|-| SW | 1.0 A | 49.8 A/mm2 | F.Cu at (113.9, 90.5), beside U1.2 |-| GND | 1.0 A | 13.8 A/mm2 | F.Cu at (112.1, 91.3) |-| VOUT | 1.0 A | 13.7 A/mm2 | F.Cu at (120.7, 90.1) |-| VIN | 0.6 A | 11.2 A/mm2 | F.Cu at (112.7, 89.1) |+| net | load | copper carrying it | vias | peak current density | where |+|---|---|---|---|---|---|+| SW | 1.0 A | 20 mm2 patch on F.Cu | 0 | 49.8 A/mm2 | F.Cu at (113.9, 90.5), beside U1.2 |+| GND | 1.0 A | 798 mm2 on both layers | 13 | 14.0 A/mm2 | F.Cu at (112.1, 91.3) |+| VIN | 0.6 A | 111 mm2 | 0 | 13.8 A/mm2 | F.Cu at (110.1, 84.5) |+| VOUT | 1.0 A | 103 mm2 | 6 | 13.2 A/mm2 | B.Cu at (122.9, 88.5) | -The Joule heating in the copper is about 2 mW in total, so the copper itself is not a heat source. The heat comes from U1 and L1.--aiflow's own current check (IPC-2221 on each loaded net's narrowest conductor, the pours and via capacity) also passes:--| net | copper carrying the load | vias | result |-|---|---|---|---|-| GND | 738 mm2 pour on both layers | 13 | pass |-| SW | 15 mm2 patch on F.Cu | 0 | pass |-| VIN | 109 mm2 pour on F.Cu; the narrowest track, 0.5 mm, carries 0.6 A at +4.2 C | 0 | pass |-| VOUT | 79 mm2 pour on F.Cu | 4 | pass |+The Joule heating in the copper is about 1 mW in total, so the copper itself is not a heat source. The heat comes from U1 and L1.  ## Thermal: where the heat goes -![Heat flow in each copper layer: U1 sheds its 0.25 W through its GND pin into the top pour and down the thermal vias into the bottom plane; L1 spreads 0.12 W through the VOUT pour](docs/img/heat-flow.png)+![Heat flow in the F.Cu copper with the parts solid: U1 sheds its 0.25 W through its GND pin into the top pour and down the thermal vias, and L1 spreads 0.12 W through the VOUT pour](docs/img/heat-flow.png)  How each part's heat leaves, from the Fields solve (W):  | part | power | along its own copper | down its vias | through the dielectric | to air at the part | other vias | |---|---|---|---|---|---|---|-| U1 (via GND pin) | 0.25 | 0.142 | 0.066 (3 vias) | 0.024 | 0.011 | 0.009 |+| U1 (via GND pin) | 0.25 | 0.145 | 0.069 (3 vias) | 0.026 | 0.011 | 0 | | L1 (via VOUT) | 0.12 | 0.077 | 0.007 (1 via) | 0.026 | 0.011 | 0 |  U1 is a SOT-23 with no exposed pad, so its heat goes out through the pins, and mostly through GND. The GND vias Fields counts at U1 (two under U1.1, one beside C4.2) carry about a quarter of it straight into the B.Cu ground plane. -![Temperature rise over the board: still air peak +50 C, moving air peak +30 C](docs/img/temperature.png)+![Temperature rise over the board in still air: U1 +45 C, L1 +41 C, board peak +50 C](docs/img/temperature.png)  | part | still air (10 W/m2K) | moving air (25 W/m2K) | |---|---|---|-| U1, at its GND pin | +44.4 C | +24.3 C |+| U1, at its GND pin | +44.7 C | +24.6 C | | L1, at its VOUT pad | +41.4 C | +21.0 C |-| board peak | +49.9 C | +29.8 C |+| board peak | +50.2 C | +30.0 C | -## The approved budget: 55 C, still air, junction based+## The thermal budget: 55 C, still air, junction based -The first spec set a 30 C rise budget, to keep the junction under 85 C at a 55 C ambient. The Fields solve failed that budget in still air (U1 +44 C, L1 +41 C).+The first target was a 30 C rise, to keep the junction under 85 C at a 55 C ambient. In still air the solve shows U1 +45 C and L1 +41 C, over that target. -We then checked whether better copper could close the gap, and found the limit is the board's area, not the layout:+Better copper cannot close that difference. The limit is the board's area, not the layout:  - A 28 x 20 mm board losing 0.37 W to still air on both faces rises about **+33 C on average even with perfect copper** (0.37 W / (10 W/m2K x 2 x 560 mm2)). - Adding 8 more GND vias at the nearest free spots (2.6 to 3.8 mm from U1.1) changed U1 by **0 C** in the Fields solve. -So 30 C in still air cannot be reached on a molecule this size. On 2026-09-29 John approved option 2: a **junction-based budget of 55 C pin/tab rise in still air**. The reasoning:+So 30 C in still air cannot be reached on a molecule this size. The board uses a **junction-based budget of 55 C pin/tab rise in still air** instead. The reasoning:  | step | value | |---|---|-| U1 rise at its GND pin, still air | +44 C |+| U1 rise at its GND pin, still air | +45 C | | pin to junction: psi_JB 33.7 C/W (datasheet) x 0.25 W | about +8 C |-| U1 junction | about ambient + 52 C |-| at a 40 C ambient | about 92 C, 33 C under the 125 C rating |+| U1 junction | about ambient + 53 C |+| at a 40 C ambient | about 93 C, 32 C under the 125 C rating | | L1 rise, still air | +41 C, inside its -40 to +125 C rating including self-heating |-| moving air (25 W/m2K) | both under 30 C (U1 +24 C, L1 +21 C) |--With the 55 C budget, the final solve reports 0 issues. Note that the approved figure assumes a 40 C ambient, where the first budget assumed 55 C. In moving air, both parts are under the original 30 C budget.+| moving air (25 W/m2K) | both under 30 C (U1 +25 C, L1 +21 C) | -aiflow's copper-area heuristic also passes: U1 is about 35 C/W into 738 mm2 of GND copper with 13 vias (+8.7 C), and L1 is about 327 C/W into 79 mm2 of VOUT copper (+39.2 C). The field solve is the stricter of the two for U1, so it sets the budget.+With the 55 C budget, the final solve reports 0 issues. Note that this budget assumes a 40 C ambient, where the first target assumed 55 C. In moving air, both parts are under the original 30 C target.  ## Files  | file | what | |---|---|-| `aiflow/run/fields/fields.json` | the Fields solve: per-net current, per-chip heat paths, method |-| `aiflow/run/drawings/*.png` | the three drawings on this page |-| `aiflow/spec.json` | loads, hot parts, the approved budget and its note |+| `aiflow/spec.json` | the loads, hot parts, copper thickness and thermal budget the solve used |

@@ -1,178 +1,178 @@-{
- "placed": [
-  {
-   "ref": "U1",
-   "fp": "Package_TO_SOT_SMD:TSOT-23-6",
-   "where": "staging"
-  },
-  {
-   "ref": "L1",
-   "fp": "buck12v5v:L_Abracon_AMPLH5030S",
-   "where": "staging"
-  },
-  {
-   "ref": "C1",
-   "fp": "Capacitor_SMD:CP_Elec_6.3x5.8",
-   "where": "staging"
-  },
-  {
-   "ref": "C2",
-   "fp": "Capacitor_SMD:C_1206_3216Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "C3",
-   "fp": "Capacitor_SMD:C_1206_3216Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "C4",
-   "fp": "Capacitor_SMD:C_0603_1608Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "C5",
-   "fp": "Capacitor_SMD:C_0603_1608Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "C6",
-   "fp": "Capacitor_SMD:C_0805_2012Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "C7",
-   "fp": "Capacitor_SMD:C_0805_2012Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "C8",
-   "fp": "Capacitor_SMD:C_0805_2012Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "C9",
-   "fp": "Capacitor_SMD:C_0402_1005Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "R1",
-   "fp": "Resistor_SMD:R_0402_1005Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "R2",
-   "fp": "Resistor_SMD:R_0402_1005Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "R3",
-   "fp": "Resistor_SMD:R_0402_1005Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "R4",
-   "fp": "Resistor_SMD:R_0402_1005Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "R5",
-   "fp": "Resistor_SMD:R_0402_1005Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "R6",
-   "fp": "Resistor_SMD:R_0402_1005Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "D1",
-   "fp": "LED_SMD:LED_0603_1608Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "MP1",
-   "fp": "Molecule:MachinePinMediumShort",
-   "where": "fixed"
-  },
-  {
-   "ref": "MP2",
-   "fp": "Molecule:MachinePinMediumShort",
-   "where": "fixed"
-  },
-  {
-   "ref": "MP3",
-   "fp": "Molecule:MachinePinMediumShort",
-   "where": "fixed"
-  },
-  {
-   "ref": "MP4",
-   "fp": "Molecule:MachinePinMediumShort",
-   "where": "fixed"
-  },
-  {
-   "ref": "J1",
-   "fp": "Molecule:MachineContactMedium",
-   "where": "fixed"
-  },
-  {
-   "ref": "J2",
-   "fp": "Molecule:MachineContactMedium",
-   "where": "fixed"
-  },
-  {
-   "ref": "J3",
-   "fp": "Molecule:MachineContactMedium",
-   "where": "fixed"
-  },
-  {
-   "ref": "J4",
-   "fp": "Molecule:MachineContactMedium",
-   "where": "fixed"
-  },
-  {
-   "ref": "J5",
-   "fp": "Molecule:MachineContactMedium",
-   "where": "fixed"
-  },
-  {
-   "ref": "J6",
-   "fp": "Molecule:MachineContactMedium",
-   "where": "fixed"
-  },
-  {
-   "ref": "TP1",
-   "fp": "TestPoint:TestPoint_Pad_D1.0mm",
-   "where": "staging"
-  },
-  {
-   "ref": "TP2",
-   "fp": "TestPoint:TestPoint_Pad_D1.0mm",
-   "where": "staging"
-  },
-  {
-   "ref": "TP3",
-   "fp": "TestPoint:TestPoint_Pad_D1.0mm",
-   "where": "staging"
-  },
-  {
-   "ref": "TP4",
-   "fp": "TestPoint:TestPoint_Pad_D1.0mm",
-   "where": "staging"
-  },
-  {
-   "ref": "R7",
-   "fp": "Resistor_SMD:R_0402_1005Metric",
-   "where": "staging"
-  },
-  {
-   "ref": "R8",
-   "fp": "Resistor_SMD:R_0402_1005Metric",
-   "where": "staging"
-  }
- ],
- "warnings": [],
- "board": "C:\\Users\\john\\Documents\\buck-12v5v-molecule\\kicad\\buck-12v5v-molecule.kicad_pcb",
- "nets": 10,
- "footprints": 34
+{+ "placed": [+  {+   "ref": "U1",+   "fp": "Package_TO_SOT_SMD:TSOT-23-6",+   "where": "staging"+  },+  {+   "ref": "L1",+   "fp": "buck12v5v:L_Abracon_AMPLH5030S",+   "where": "staging"+  },+  {+   "ref": "C1",+   "fp": "Capacitor_SMD:CP_Elec_6.3x5.8",+   "where": "staging"+  },+  {+   "ref": "C2",+   "fp": "Capacitor_SMD:C_1206_3216Metric",+   "where": "staging"+  },+  {+   "ref": "C3",+   "fp": "Capacitor_SMD:C_1206_3216Metric",+   "where": "staging"+  },+  {+   "ref": "C4",+   "fp": "Capacitor_SMD:C_0603_1608Metric",+   "where": "staging"+  },+  {+   "ref": "C5",+   "fp": "Capacitor_SMD:C_0603_1608Metric",+   "where": "staging"+  },+  {+   "ref": "C6",+   "fp": "Capacitor_SMD:C_0805_2012Metric",+   "where": "staging"+  },+  {+   "ref": "C7",+   "fp": "Capacitor_SMD:C_0805_2012Metric",+   "where": "staging"+  },+  {+   "ref": "C8",+   "fp": "Capacitor_SMD:C_0805_2012Metric",+   "where": "staging"+  },+  {+   "ref": "C9",+   "fp": "Capacitor_SMD:C_0402_1005Metric",+   "where": "staging"+  },+  {+   "ref": "R1",+   "fp": "Resistor_SMD:R_0402_1005Metric",+   "where": "staging"+  },+  {+   "ref": "R2",+   "fp": "Resistor_SMD:R_0402_1005Metric",+   "where": "staging"+  },+  {+   "ref": "R3",+   "fp": "Resistor_SMD:R_0402_1005Metric",+   "where": "staging"+  },+  {+   "ref": "R4",+   "fp": "Resistor_SMD:R_0402_1005Metric",+   "where": "staging"+  },+  {+   "ref": "R5",+   "fp": "Resistor_SMD:R_0402_1005Metric",+   "where": "staging"+  },+  {+   "ref": "R6",+   "fp": "Resistor_SMD:R_0402_1005Metric",+   "where": "staging"+  },+  {+   "ref": "D1",+   "fp": "LED_SMD:LED_0603_1608Metric",+   "where": "staging"+  },+  {+   "ref": "MP1",+   "fp": "Molecule:MachinePinMediumShort",+   "where": "fixed"+  },+  {+   "ref": "MP2",+   "fp": "Molecule:MachinePinMediumShort",+   "where": "fixed"+  },+  {+   "ref": "MP3",+   "fp": "Molecule:MachinePinMediumShort",+   "where": "fixed"+  },+  {+   "ref": "MP4",+   "fp": "Molecule:MachinePinMediumShort",+   "where": "fixed"+  },+  {+   "ref": "J1",+   "fp": "Molecule:MachineContactMedium",+   "where": "fixed"+  },+  {+   "ref": "J2",+   "fp": "Molecule:MachineContactMedium",+   "where": "fixed"+  },+  {+   "ref": "J3",+   "fp": "Molecule:MachineContactMedium",+   "where": "fixed"+  },+  {+   "ref": "J4",+   "fp": "Molecule:MachineContactMedium",+   "where": "fixed"+  },+  {+   "ref": "J5",+   "fp": "Molecule:MachineContactMedium",+   "where": "fixed"+  },+  {+   "ref": "J6",+   "fp": "Molecule:MachineContactMedium",+   "where": "fixed"+  },+  {+   "ref": "TP1",+   "fp": "TestPoint:TestPoint_Pad_D1.0mm",+   "where": "staging"+  },+  {+   "ref": "TP2",+   "fp": "TestPoint:TestPoint_Pad_D1.0mm",+   "where": "staging"+  },+  {+   "ref": "TP3",+   "fp": "TestPoint:TestPoint_Pad_D1.0mm",+   "where": "staging"+  },+  {+   "ref": "TP4",+   "fp": "TestPoint:TestPoint_Pad_D1.0mm",+   "where": "staging"+  },+  {+   "ref": "R7",+   "fp": "Resistor_SMD:R_0402_1005Metric",+   "where": "staging"+  },+  {+   "ref": "R8",+   "fp": "Resistor_SMD:R_0402_1005Metric",+   "where": "staging"+  }+ ],+ "warnings": [],+ "board": "buck-12v5v-molecule.kicad_pcb",+ "nets": 10,+ "footprints": 34 }\ No newline at end of file