12 V to 5 V / 1 A Buck Molecule (TPS54202)

@@ -1,147 +0,0 @@-# The adom-aiflow run: timings, who did what, and the gaps--The board was laid out in one measured adom-aiflow run. The engine was `claude-opus-5.5` and the test box was ConfRoomROG, running KiCad 10.0.5 through the Adom KiCad Bridge. aiflow keeps a ledger of every command, reply, step change, clip and outcome (`aiflow/run/run.jsonl`, summarised in `run.json`). This page reads from that ledger.--- Every step's video clip: [build clips](clips.md)-- The report aiflow generated for the run: [run report](runs/buck-12v5v-molecule-claude-opus-5-5-20260929-0039/README.md)--## The clock--| event | time (UTC, 2026-09-29) |-|---|---|-| prompt (clock starts) | 00:39:00 |-| `start` (first aiflow command, board exists) | 02:09:55 |-| `finish` accepted | 15:17:30 |-| **prompt to finish** | **878.5 min** |--`start` was given the prompt time, so the first 91 minutes before any board existed count toward the run: reading the brief, choosing parts, the calculations, the ngspice simulation, and the schematic and netlist. Without that, the pre-board work would have gone untimed.--## Step timings--In the ledger, "thinking" is the time between aiflow's previous reply and the AI's next command. "Binary" is the time aiflow's own commands ran. Wall is the sum of the two.--| step | visits | returns | turns | thinking (min) | binary (min) | wall (min) |-|---|---|---|---|---|---|---|-| intake | 1 | 0 | 4 | 91.9 | 1.0 | 92.9 |-| components | 1 | 0 | 2 | 4.4 | 0.1 | 4.5 |-| libraries | 1 | 0 | 1 | 8.6 | 2.9 | 11.4 |-| models | 1 | 0 | 3 | 5.4 | 0.9 | 6.3 |-| placement | 1 | 0 | 11 | 4.3 | 10.6 | 14.9 |-| routing | 2 | 1 | 21 | 0.0 | 91.2 | 91.2 |-| pours | 2 | 1 | 27 | 0.0 | 6.1 | 6.1 |-| current | 1 | 0 | 6 | 0.0 | 0.1 | 0.1 |-| thermal | 2 | 0 | 14 | 0.0 | 11.5 | 11.5 |-| fields | 1 | 0 | 3 | 0.0 | 9.0 | 9.0 |-| nets | 1 | 0 | 3 | 0.0 | 1.7 | 1.7 |-| silkscreen | 1 | 0 | 2 | 0.0 | 0.1 | 0.1 |-| 3d | 1 | 0 | 3 | 0.0 | 12.1 | 12.1 |-| **total** | | **2** | **101** | **114.6** | **147.4** | **262.0** |--The steps add up to about 262 minutes. Most of the remaining time in the 878.5 is an idle gap that the ledger does not assign to any step: about 8.4 hours overnight, between 03:11 and 11:32 UTC.--The two returns were both triggered by the Fields solve:--1. **Back to routing:** "the VOUT Kelvin sense runs 10 mm on B.Cu under the input caps (y=86.4), slicing the GND plane under the hot loop; re-route it along the top edge".-2. **Back to pours:** "SW neck 215 A/mm2 at U1.2; U1 +51 C still air (Kelvin keepouts fenced U1.1 off the GND pour, no thermal vias); add SW patch, solid GND + thermal vias at U1.1, keepouts on the sense layer only".--A third visit to pours followed `analyze current`, which refused a 60 A/mm2 throat in the SW patch. [Board](board.md) and [thermal and current](thermal-current.md) tell those stories.--Time spent inside aiflow's own stages:--| stage | minutes |-|---|---|-| land route (48 traces, live, one undo step each) | 9.9 |-| tour fields (Adom Fields walkthrough, filmed) | 4.4 |-| land pours | 3.2 |-| tour 3d (31 view commands, filmed) | 1.5 |-| land vias | 1.0 |-| gate (offline KiCad DRC) | 0.9 |-| measure (native copper readback) | 0.6 |-| place land (24 parts) | 0.4 |-| tour nets | 0.4 |-| route, pour, models, analyze current, analyze thermal | under 0.1 each |--## What aiflow did and what the AI did--aiflow ran as the instrument, the gates and the hands. The engineering judgement came from the AI.--| aiflow (the binary) | the AI |-|---|---|-| the ledger and the clock from the prompt; a video clip and start/end screenshots for every step | the brief, the requirements, part choice and the stock checks |-| the component and model audit (34 footprints: 30 with models, 4 that correctly have none) | the datasheet calculations (`design/calcs.py`) and the ngspice loop and transient models |-| `place pack` / `place check` / `place land`: legal spots, DRC on the moved board, live landing | TI's PSpice model run and the comparison against it |-| the grid router (48 traces, 0 unrouted after 5 passes) | the schematic, the netlist and the molecule outline, pins and contacts |-| the offline gate (KiCad DRC, 0 new errors, 0 unconnected) | `aiflow/spec.json`: wide nets, Kelvin taps, loads, hot parts, pours |-| live landing of traces, vias and pours through the bridge, one undo step each | the placement itself (`wishes.json`) |-| `measure`: copper per layer read back from KiCad's own fills | the routing rework: FB, FBM, VOUT and the LED rerouted by hand, the feedback chain turned 180 deg |-| `analyze current` / `analyze thermal`, with the Adom Fields solve | the SW patch polygon, the solid joints and the three hand-placed GND vias |-| the filmed tours: Fields, nets, 3D | the resume plan for the interrupted `land route`, the renamed Kelvin keepouts |-| `finish`: refuses until 0 unconnected, 0 new errors, pours landed, both analyses passing, copper measured | the silkscreen (19 labels via `tools/silk_place.py`), the C1 model rotation fix, the three drawings |-| | `tools/kicad-cli-remote`, so the gate could use the desktop's KiCad 10 |--## Gaps found in aiflow--Everything in this run that aiflow did not guide, gate or measure was logged as it happened (`AIFLOW-GAPS.md`), so each gap can become an issue or a PR on adom/adom-aiflow. Each gap is tagged by where the fix belongs: a **skill** (judgement the AI should follow), a **gate** (a check the binary should enforce), **instrument** (something the binary should measure), or **hands** (native landing through the bridge).--| # | gap | belongs in | status |-|---|---|---|---|-| 1 | the clock needs a board, so pre-board work is untimed | instrument | **closed in 0.1.37** |-| 2 | no intake step to turn a brief into requirements | skill | skill in 0.1.34 (`aiflow-intake`) |-| 3 | the sourcing profile should follow the fab target | skill + gate | **closed in 0.1.37** |-| 4 | no guided parts-search pass | skill + gate | **closed in 0.1.37** |-| 5 | nothing points at Adom stocked parts | skill + gate | **closed in 0.1.37** |-| 6 | no step records design equations next to values | skill | skill in 0.1.34 (`aiflow-circuit-design`) |-| 7 | no simulation step or gate | skill + gate | **closed in 0.1.37** |-| 8 | no schematic-to-board path or netlist equivalence check | gate | **closed in 0.1.37** |-| 9 | aiflow does not know the molecule format | skill + gate | **closed in 0.1.37** |-| 10 | DRC does not load the target fab's rules | gate | **closed in 0.1.37** |-| 12 | no vendor-model (PSpice) simulation step | skill + gate + hands | **closed in 0.1.37** |-| 13 | vendor logins: get them from the vault, never ask the human | skill | skill in 0.1.34 (`aiflow-credentials`) |-| 14 | vendor sign-ups work in the user's real browser | skill | skill in 0.1.34 (`aiflow-credentials`) |-| 15 | PSpice model access needs an approval wait | skill | skill in 0.1.34 (`aiflow-credentials`) |-| 16 | pup drops when a verb carries a secret | bug (pup-bridge) | filed: adom/pup-bridge#127 |-| 17 | `send_files` to a `.pretty` folder writes a file | bug (adom-bridge) | filed: adom/adom-bridge#220 |-| 18 | never use chipsmith; model sourcing order | skill | skill in 0.1.34 (`aiflow-sourcing`) |-| 19 | generate STEP geometry on the shared step2glb service | skill | skill in 0.1.34 (`aiflow-sourcing`) |-| 20 | search manufacturer CAD by series; check every model is Z-up | skill + gate | **closed in 0.1.37** |-| 21 | no native kicad-cli in the container | instrument / gate | the remote wrapper now ships with 0.1.33 |-| 22 | a stale KiCad 7 kicad-cli wins silently | gate | **fixed in 0.1.33** |-| 23 | `land route` is not resumable | hands | **closed in 0.1.37** |-| 24 | duplicate Kelvin keepout names refused by the bridge | bug | **fixed in 0.1.33** |-| 25 | the router has no layer policy for 2-layer power boards | skill + router | **closed in 0.1.37** |-| 26 | the packer picks rotations that knot a divider chain | skill + pack scoring | **closed in 0.1.37** |-| 27 | Kelvin keepouts on both layers and up to the power pin | bug | **fixed in 0.1.33** |-| 28 | thermal vias for small pins land inside the pad | bug | **fixed in 0.1.33** |-| 29 | a planned GND via landed as SW; clip files missing from the manifest | bug | **closed in 0.1.37** |-| 30 | no live clips sub-readme | instrument + skill | **closed in 0.1.37** |-| 31 | `tour fields` opens a localhost proxy on the wrong box | bug | **closed in 0.1.37** |-| 32 | silkscreen text verb contract and minimum height | skill + bridge | skill in 0.1.34; bridge side filed on adom/kicad-bridge#104 |-| 33 | `finish` after adopting a routed board | bug | **closed in 0.1.37** |-| 34 | `compose` could not assemble the video from a relative run path | bug | **fixed in 0.1.35** |-| 35 | clip pulls that fail silently (four clips lost) | bug | **closed in 0.1.37** |-| 36 | `capture start` used a dead window handle after the editor was reopened | bug | **fixed in 0.1.38** |-| 37 | the silkscreen text verb's `rotation` field and stroke cap were undocumented | docs | **documented in 0.1.38** (aiflow-silkscreen, aiflow-power-layout) |-| 38 | a 2.7 GB step clip could not be pulled in one piece | bug | **fixed in 0.1.38** (pulled in 200 MB parts) |-| 39 | the silkscreen dashboard replay needs a Hydrogen tab on the user's machine | skill | open (board.json and events.jsonl kept in the run for a later replay) |-| 40 | the ICs' models had no MPN mark, and the etch service alone repaints the part and writes across the short axis | bug + default | **fixed in 0.1.39** (`adom-aiflow-etch`, default on for ICs, finish check) |-| 41 | component pages had plain heroes instead of the annotated, etched eda-component-hero art | skill | **skills fixed in 0.1.39** |-| 42 | a second run's report push overwrote the first run's clips page | bug | **fixed in 0.1.40** |-| 43 | the MPN mark was 3D text, and its colour was not stored | bug | **fixed in 0.1.41 and 0.1.42** (flat mark, 80 % fewer triangles) |-| 44 | the etch tool installed OpenCascade locally without asking | rule | **fixed in 0.1.41** (opt-in only) |--Ten companion skills from this run shipped in adom-aiflow 0.1.34 (2026-09-29), and 0.1.37 (2026-09-30) closed every remaining gap in the binary. Its new `planeUnder` gate then found one thing on this board: an EN via and part of the VOUT sense trace on B.Cu under the input hot loop (see the gap log).--### Fixed in adom-aiflow 0.1.33--Published 2026-09-29 (source 64820bb):--| gap | fix |-|---|---|-| 22 | `run_drc` takes only a kicad-cli that supports `pcb drc --refill-zones`; the error names `adom-aiflow-kicad-cli-remote`, which now installs with the package |-| gate phantom errors | with a native kicad-cli, the gate refills zones natively and skips the raster fill. On this board, 242 phantom errors became 0 |-| 33 (analyses) | `analyze current` and `analyze thermal` merge the board's own tracks and vias into the plan, so an adopted, routed board is analysed on its real copper. `route` still re-plans every trace (open) |-| 24 | Kelvin tap keepouts are numbered per net |-| 27 | tap keepouts sit on the sense segment's own layer (both layers only at its vias) and stop short of the power pin |-| 28 | thermal vias for small pins go just outside the pad (0.6 / 0.3 mm), clear of other nets, stitch vias and board vias; `pour` reports how many fit |--Still open: 23 (resuming `land route`), 25 (router layer policy), 26 (pack rotations for chains), 29 (via net enforcement, clip manifest), 30 (clips sub-readme in the binary), 31 (`tour fields` on a localhost proxy), 32 (silk text contract) and 33 (route only the unconnected items).