65% MX Keyboard (soldered)

@@ -60,4 +60,6 @@ Every step of the build, in order, each with its own page of evidence (checks, s  **8. Routing**: every trace routed, DRC clean. [The evidence](steps/08-routing/README.md) +**9. Heatsink vias**: via arrays under the hot parts. [The evidence](steps/09-thermal-vias/README.md)+ <!-- /aiflow:steps -->

@@ -0,0 +1,34 @@+# Step 9: Heatsink vias++Heatsink vias where the heat is: for every part that dissipates real power (the regulator, the inductor, the catch diode, the FETs), an array of vias in its thermal pad or the copper it dumps heat into, stitched to the ground or the plane on the other side, sized and counted from its dissipation; the AI reviews the plan and the binary lands it.++## Visits++- 2026-11-09T03:53:41Z++## What the binary checked++### thermal-vias++- **acked**: 0 item(s)+- **countedOn**: live board (kicad_routing_state)+- **landed**: 0+- **leftOutAcked**: +- **short**: 0 item(s)++### thermal-vias-plan++- **boardZones**: 0 item(s)+- **parts**: 0 item(s)+- **plan**: aiflow-run/plan-thermal-vias.json+- **pourFreshness**: 0 item(s)++## Screenshots and drawings++**start**++![start](shot-thermal-vias-1-start.png)++**visit 1-start**++![visit 1-start](shot-thermal-vias-1-start.png)

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