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ZXMP6A18DN8TA

TECH PUBLIC · MOSFETs · SOP-8

ZXMP6A18DN8TA from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of MOSFET 1 (P-channel); VDSS -60V, ID -3.8A per device.
2 G1 input Gate of MOSFET 1; VGSS rating ±20V, threshold -1.0V to -3.0V at ID=-250µA.
3 S2 passive Source of MOSFET 2 (P-channel); VDSS -60V, ID -3.8A per device.
4 G2 input Gate of MOSFET 2; VGSS rating ±20V, threshold -1.0V to -3.0V at ID=-250µA.
5 D2 passive Drain of MOSFET 2; VDSS -60V, continuous ID -3.8A, pulsed IDM -16A.
6 D2 passive Drain of MOSFET 2, internally common with pin 5; VDSS -60V, continuous ID -3.8A.
7 D1 passive Drain of MOSFET 1, internally common with pin 8; VDSS -60V, continuous ID -3.8A.
8 D1 passive Drain of MOSFET 1; VDSS -60V, continuous ID -3.8A, pulsed IDM -16A.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: ZXMP6A18DN8TA
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: zxmp6a18dn8ta-etched.step / zxmp6a18dn8ta-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); zxmp6a18dn8ta.step / zxmp6a18dn8ta.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (5 pp, sha256 1e9b69893bfaf2ac, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF